Jerry Van Baren wrote:
I suspect your 8349E-mITX is configured to "boothigh" (BMS = 1, also known as HRCWH_FROM_0XFFF00100) so the u-boot image starts at 0xFFF00000 rather than at the start of flash (nominally 0xFE000000). In this case you should find the magic and version string starting at 0xFFF00040. Of course, in the .bin/.srec/whatever file, it should be at offset 0x40.
Yes, that's correct.
That is one of the advantages of "bootlow" - the HRCW from u-boot is placed at the start of flash and thus is used. With "boothigh" , the HRCW that is part of u-boot is in the "wrong place" and thus is not used. (Another advantage of "bootlow" is that you don't have to dedicate 1MB of flash for the u-boot image.)
The original code from our BSP had only boothigh, so that's how I left it. I guess I should test lowboot as an option.
Looking at include/configs/MPC8349ITX.h, if PCI_64BIT is defined it does a lowboot, otherwise it does a highboot (which seems odd to me, but people tell me I'm odd and the world is normal).
I've noticed that too, and I'm trying to get answer as to why.
The "lowboot" patch is specific to the MPC8360EMDS, although it could be copy and pasted into the MPC8349ITX configuration easily enough.
Ok, if it gets accepted, I'll port it to the 8349ITX.