From: Jimmy Zhang jimmzhang@nvidia.com
At cold boot, the default voltage supplied by pmu is not high enough to support emc to run at its highest clock frequency. The code added here is to update the default vdd_core and vdd_cpu to higher values.
(Sorry if I have mangled this comment)
Signed-off-by: Simon Glass sjg@chromium.org --- board/nvidia/common/board.c | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index fbdd260..cda2417 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -30,6 +30,7 @@ #include <asm/arch/board.h> #include <asm/arch/clk_rst.h> #include <asm/arch/clock.h> +#include <asm/arch/fuse.h> #include <asm/arch/pinmux.h> #include <asm/arch/pmc.h> #include <asm/arch/pmu.h> @@ -56,6 +57,21 @@ int timer_init(void) }
/* + * Routine: power_det_init + * Description: turn off power detects + */ +static void power_det_init(void) +{ +#if defined(CONFIG_TEGRA2) + struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; + + /* turn off power detects */ + writel(0, &pmc->pmc_pwr_det_latch); + writel(0, &pmc->pmc_pwr_det); +#endif +} + +/* * Routine: board_init * Description: Early hardware init. */ @@ -88,6 +104,8 @@ int board_init(void) /* prepare the WB code to LP0 location */ warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); #endif + + power_det_init(); #ifdef CONFIG_TEGRA2_I2C i2c_init_board();