In case the i.MX8MP DHCOM rev.100 has been populated on the PDK3 carrier board, the on-SoM PHY PHYAD1 signal has been pulled high by the carrier board and changed the PHY MDIO address from 5 to 7. This has been fixed on production rev.200 SoM by additional buffer on the SoM PHYAD/LED signals, remove the workaround.
Signed-off-by: Marek Vasut marex@denx.de --- Cc: "NXP i.MX U-Boot Team" uboot-imx@nxp.com Cc: Algapally Santosh Sagar santoshsagar.algapally@amd.com Cc: Fabio Estevam festevam@gmail.com Cc: Mayuresh Chitale mchitale@ventanamicro.com Cc: Oleksandr Suvorov oleksandr.suvorov@foundries.io Cc: Ovidiu Panait ovpanait@gmail.com Cc: Roger Quadros rogerq@kernel.org Cc: Simon Glass sjg@chromium.org Cc: Stefano Babic sbabic@denx.de Cc: u-boot@dh-electronics.com --- V2: Rebase and collect the patches in one series --- arch/arm/dts/imx8mp-dhcom-pdk3.dts | 4 ---- 1 file changed, 4 deletions(-)
diff --git a/arch/arm/dts/imx8mp-dhcom-pdk3.dts b/arch/arm/dts/imx8mp-dhcom-pdk3.dts index c5f0607f43b..867d238f2b5 100644 --- a/arch/arm/dts/imx8mp-dhcom-pdk3.dts +++ b/arch/arm/dts/imx8mp-dhcom-pdk3.dts @@ -227,10 +227,6 @@ }; };
-ðphy0g { - reg = <7>; -}; - &fec { /* Second ethernet */ pinctrl-0 = <&pinctrl_fec_rgmii>; phy-handle = <ðphypdk>;