From: Tien Fong Chee tien.fong.chee@intel.com
These series of patches enable peripheral bitstream being programmed into FPGA to get the DDR up running. This's also called early IO release, because the peripheral bitstream is only initializing FPGA IOs, PLL, IO48 and DDR.
Once DDR is up running, core bitstream from MMC which contains user FPGA design would be loaded into DDR location. socfpga loadfs would be called to program core bitstream into FPGA and entering user mode.
Lastly, u-boot-dtb.img from MMC FAT partition would be loaded to DDR, and up running from there.
For this whole mechanism to work, the SDMMC flash layout would be designed as shown in below:
RAW partition: 1. spl_w_dtb-mkpimage.bin mkpimage -hv 1 -o spl/spl_w_dtb-mkpimage.bin spl/u-boot-spl-dtb.bin spl/u-boot-spl-dtb.bin spl/u-boot-spl-dtb.bin spl/u-boot-spl-dtb.bin
FAT partition contains: Bitstreams ---------- Early IO release method is recommended for the sake of performance, improve up to 86% compare to full RBF.
1. ghrd_10as066n2.periph.rbf.mkimage mkimage -A arm -T firmware -C none -O u-boot -a 0 -e 0 -n "RBF" -d ghrd_10as066n2.periph.rbf ghrd_10as066n2.periph.rbf.mkimage
2. ghrd_10as066n2.core.rbf.mkimage mkimage -A arm -T firmware -C none -O u-boot -a 0 -e 0 -n "RBF" -d ghrd_10as066n2.core.rbf ghrd_10as066n2.core.rbf.mkimage
OR
1. ghrd_10as066n2.rbf.mkimage (full RBF) mkimage -A arm -T firmware -C none -O u-boot -a 0 -e 0 -n "RBF" -d ghrd_10as066n2.rbf ghrd_10as066n2.rbf.mkimage
U-Boot image ------------ 3. u-boot-dtb.img
For the testing purpose, these two patches are required to apply 1st before applying this series of patches. 1. [U-Boot] [PATCH] misc: fs_loader: Switching private data allocation to DM auto allocation https://www.mail-archive.com/u-boot@lists.denx.de/msg308954.html Reviewed-by: Simon Glass s...@chromium.org
2. [U-Boot] [PATCH v2] Add support for initializing MMC https://www.mail-archive.com/u-boot@lists.denx.de/msg310532.html Version 2 under review.
This series is working on top of u-boot.git - http://git.denx.de/u-boot.git .
Marek Vasut (1): ARM: socfpga: Synchronize the configuration for A10 SoCDK
Tien Fong Chee (5): ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK ARM: dts: socfpga: Add missing SDMMC reset spl : socfpga: Implement fpga bitstream loading with socfpga loadfs
arch/arm/dts/socfpga_arria10.dtsi | 1 + arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 18 + .../include/mach/fpga_manager_arria10.h | 40 ++- arch/arm/mach-socfpga/spl_a10.c | 46 +++- configs/socfpga_arria10_defconfig | 46 ++- .../fpga/altera-socfpga-a10-fpga-mgr.txt | 21 + drivers/fpga/Kconfig | 9 + drivers/fpga/socfpga_arria10.c | 396 +++++++++++++++++++- 8 files changed, 558 insertions(+), 19 deletions(-)