Wolfgang Denk wrote:
I have to admit that I don't like the impact on the memory footprint of the driver.
I can't think of any other way to support programmable I2C bus speeds. Even if we did something like this in the board header files:
#define CFG_FSL_I2C_DFSR 43 #define CFG_FSL_I2C_FDR 3
We still would not be able to support the "i2c speed" command.
I did my best to make fsl_i2c_speed_map[] as small as possible. It should be smaller than 300 bytes.
Besides, this code is for Freescale's high-end SOCs. Memory footprint is critical.
And to make sure I understand this correctly: is it correct to assume that this driver has never been tested with environment in a EEPROM?
Do you mean the fsl_i2c.c driver itself, or the driver with my patch? I don't know if the driver itself has been tested, but I did not test my driver with any major data in the EEPROM. If it turns out that the new values for the I2C bus speed registers are too aggressive, then they can be tuned. Prior to this patch, the values couldn't be tuned without hacking common code.