As written in comment, P2020 has two possible SD switch configurations. Extend code to detect both of them.
Signed-off-by: Pali Rohár pali@kernel.org --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 4 ++++ include/configs/p1_p2_rdb_pc.h | 3 ++- 2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 186887336354..29502a5c05c2 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -207,6 +207,10 @@ int checkboard(void) puts("rom_loc: "); if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) { puts("sd"); +#ifdef __SW_BOOT_SD2 + } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD2) { + puts("sd"); +#endif #ifdef __SW_BOOT_SPI } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) { puts("spi"); diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 370772053e63..ecc6e0c644bf 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -60,7 +60,8 @@ #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xc8 #define __SW_BOOT_SPI 0x28 -#define __SW_BOOT_SD 0x68 /* or 0x18 */ +#define __SW_BOOT_SD 0x68 +#define __SW_BOOT_SD2 0x18 #define __SW_BOOT_NAND 0xe8 #define __SW_BOOT_PCIE 0xa8 #define CONFIG_SYS_L2_SIZE (512 << 10)