On Fri, 24 Jul 2020 at 04:09, Stefan Roese sr@denx.de wrote:
From: Suneel Garapati sgarapati@marvell.com
Adds support for Core 0 watchdog poke on OcteonTX and OcteonTX2 platforms.
Signed-off-by: Suneel Garapati sgarapati@marvell.com Signed-off-by: Stefan Roese sr@denx.de
Changes in v1:
- Change patch subject
- Remove inclusion of common.h
- Remove global wdt_dev as its unused
- Remove #ifdef's
- Remove optional fixed register access - only use address passed via DT while probing
- Use dev_remap_addr() instead of dev_read_addr_index()
drivers/watchdog/Kconfig | 10 ++++++ drivers/watchdog/Makefile | 1 + drivers/watchdog/octeontx_wdt.c | 57 +++++++++++++++++++++++++++++++++ 3 files changed, 68 insertions(+) create mode 100644 drivers/watchdog/octeontx_wdt.c
Reviewed-by: Simon Glass sjg@chromium.org
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index bf06180cdd..981b33355d 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -139,6 +139,16 @@ config WDT_MTK The watchdog timer is stopped when initialized. It performs full SoC reset.
+config WDT_OCTEONTX
bool "OcteonTX core watchdog support"depends on WDT && (ARCH_OCTEONTX || ARCH_OCTEONTX2)default y if WDT && ARCH_OCTEONTX || ARCH_OCTEONTX2imply WATCHDOGhelpThis enables OcteonTX watchdog driver, which can befound on OcteonTX/TX2 chipsets and inline with driver model.Only supports watchdog reset.config WDT_OMAP3 bool "TI OMAP watchdog timer support" depends on WDT && ARCH_OMAP2PLUS diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 519bbd3a40..fbba0ca386 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o obj-$(CONFIG_WDT_MTK) += mtk_wdt.o +obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o obj-$(CONFIG_WDT_SP805) += sp805_wdt.o obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o diff --git a/drivers/watchdog/octeontx_wdt.c b/drivers/watchdog/octeontx_wdt.c new file mode 100644 index 0000000000..a9c29ef26a --- /dev/null +++ b/drivers/watchdog/octeontx_wdt.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2019 Marvell International Ltd.
- */
+#include <dm.h> +#include <errno.h> +#include <wdt.h> +#include <asm/io.h>
+DECLARE_GLOBAL_DATA_PTR;
+#define CORE0_POKE_OFFSET 0x50000
+struct octeontx_wdt {
void __iomem *reg;+};
+static int octeontx_wdt_reset(struct udevice *dev) +{
struct octeontx_wdt *priv = dev_get_priv(dev);writeq(~0ULL, ((u64)priv->reg & ~0xfffffULL) | CORE0_POKE_OFFSET);
Do you actually need the mask? It seems odd that ->reg is part-way through the register set.
return 0;+}
+static int octeontx_wdt_probe(struct udevice *dev) +{
struct octeontx_wdt *priv = dev_get_priv(dev);priv->reg = dev_remap_addr(dev);if (!priv->reg)return -EINVAL;return 0;+}
+static const struct wdt_ops octeontx_wdt_ops = {
.reset = octeontx_wdt_reset,+};
+static const struct udevice_id octeontx_wdt_ids[] = {
{ .compatible = "arm,sbsa-gwdt" },{}+};
+U_BOOT_DRIVER(wdt_octeontx) = {
.name = "wdt_octeontx",.id = UCLASS_WDT,.of_match = octeontx_wdt_ids,.ops = &octeontx_wdt_ops,.priv_auto_alloc_size = sizeof(struct octeontx_wdt),.probe = octeontx_wdt_probe,+};
2.27.0