Hi Andre,
On Sat, 25 Jan 2020 at 16:18, André Przywara andre.przywara@arm.com wrote:
On 25/01/2020 16:20, Tom Rini wrote:
Hi Tom,
thanks for having a look!
On Tue, Jan 21, 2020 at 10:23:17AM +0000, Andre Przywara wrote:
From: Maxime Ripard maxime.ripard@bootlin.com
This is needed when importing mainline DTs into U-Boot, as some started using this /omit-if-no-ref/ tag, so won't compile with U-Boot's current dtc copy. This is just a cherry-pick of the patch introducing this feature. Original commit message from Maxime:
A number of platforms have a need to reduce the number of DT nodes, mostly because of two similar constraints: the size of the DT blob, and the time it takes to parse it.
As the DT is used in more and more SoCs, and by more projects, some constraints start to appear in bootloaders running from SRAM with an order of magnitude of 10kB. A typical DT is in the same order of magnitude, so any effort to reduce the blob size is welcome in such an environment.
Some platforms also want to reach very fast boot time, and the time it takes to parse a typical DT starts to be noticeable.
Both of these issues can be mitigated by reducing the number of nodes in the DT. The biggest provider of nodes is usually the pin controller and its subnodes, usually one for each valid pin configuration in a given SoC.
Obviously, a single, fixed, set of these nodes will be used by a given board, so we can introduce a node property that will tell the DT compiler to drop the nodes when they are not referenced in the tree, and as such wouldn't be useful in the targetted system.
Signed-off-by: Maxime Ripard maxime.ripard@bootlin.com Reviewed-by: Rob Herring robh@kernel.org Signed-off-by: Andre Przywara andre.przywara@arm.com
scripts/dtc/checks.c | 13 +++++++++++++ scripts/dtc/dtc-lexer.l | 7 +++++++ scripts/dtc/dtc-parser.y | 17 +++++++++++++++++ scripts/dtc/dtc.h | 4 ++++ scripts/dtc/livetree.c | 14 ++++++++++++++ 5 files changed, 55 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
Is this for SPL or U-Boot proper? I assume the former since you talk about SRAM. But changing dtc won't affect SPL at present, since the DT is not separately compiled for SPL. Of course if nodes are not needed for U-Boot proper, removing them is good and may have SPL too. But we use dtoc to drop unwanted nodes (as you probably know), and U-Boot has its own tags for indicating what nodes should be present (since everything is omitted from SPL by default).
Regards, Simon