On 09/10/2018 07:28 PM, Dalon Westergreen wrote:
Stratix10 combines the u-boot-spl image into the fpga configuration bitstream so that the SDM can load the processors memory. This process requires a hex format of the u-boot-spl image. CONFIG_SPL_TARGET is set to "spl/u-boot-spl.hex"
Signed-off-by: Dalon Westergreen dwesterg@gmail.com
include/configs/socfpga_stratix10_socdk.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h index b58f478004..91315a0031 100644 --- a/include/configs/socfpga_stratix10_socdk.h +++ b/include/configs/socfpga_stratix10_socdk.h @@ -202,6 +202,7 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
- 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
*/ +#define CONFIG_SPL_TARGET "spl/u-boot-spl.hex" #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
Applied to socfpga/master, thanks