On Tue, Jun 12, 2018 at 11:34 AM, Vipul Kumar vipul.kumar@xilinx.com wrote:
From: Michal Simek michal.simek@xilinx.com
This patch added support to read register base address from DTS file.
This patch also adding fifo_depth apart from reg.
Signed-off-by: Michal Simek michal.simek@xilinx.com Signed-off-by: Vipul Kumar vipul.kumar@xilinx.com
drivers/spi/xilinx_spi.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 8f0f32f..615106b 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -77,10 +77,6 @@ #define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0) #endif
-#ifndef CONFIG_SYS_XILINX_SPI_LIST -#define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE } -#endif
/* xilinx spi register set */ struct xilinx_spi_regs { u32 __space0__[7]; @@ -105,16 +101,14 @@ struct xilinx_spi_priv { struct xilinx_spi_regs *regs; unsigned int freq; unsigned int mode;
unsigned int fifo_depth;};
-static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST; static int xilinx_spi_probe(struct udevice *bus) { struct xilinx_spi_priv *priv = dev_get_priv(bus); struct xilinx_spi_regs *regs = priv->regs;
priv->regs = (struct xilinx_spi_regs *)xilinx_spi_base_list[bus->seq];writel(SPISSR_RESET_VALUE, ®s->srr); return 0;@@ -285,6 +279,21 @@ static const struct dm_spi_ops xilinx_spi_ops = { .set_mode = xilinx_spi_set_mode, };
+static int xilinx_spi_ofdata_to_platdata(struct udevice *bus) +{
struct xilinx_spi_priv *priv = dev_get_priv(bus);struct udevice *dev = dev_get_parent(bus);priv->regs = (struct xilinx_spi_regs *)devfdt_get_addr(bus);
Since the driver has OF_CONTROL support, better to get reg into probe and skip platdata.
debug("%s: regs=%p\n", __func__, priv->regs);priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),"fifo-size", 0);
Where this using? better to add it separate patch along with usage code.