We can reset the Soc using some CRU (clock/reset unit) register. Add support for this.
Signed-off-by: Lin Huang hl@rock-chips.com --- Chnages in v1: - clean copyright announcement
arch/arm/mach-rockchip/rk3036/Makefile | 8 +++++ arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 45 ++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) create mode 100644 arch/arm/mach-rockchip/rk3036/Makefile create mode 100644 arch/arm/mach-rockchip/rk3036/reset_rk3036.c
diff --git a/arch/arm/mach-rockchip/rk3036/Makefile b/arch/arm/mach-rockchip/rk3036/Makefile new file mode 100644 index 0000000..643c8d1 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2015 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += reset_rk3036.o + diff --git a/arch/arm/mach-rockchip/rk3036/reset_rk3036.c b/arch/arm/mach-rockchip/rk3036/reset_rk3036.c new file mode 100644 index 0000000..fefb568 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036/reset_rk3036.c @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <reset.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3036.h> +#include <asm/arch/hardware.h> +#include <linux/err.h> + +int rk3036_reset_request(struct udevice *dev, enum reset_t type) +{ + struct rk3036_cru *cru = rockchip_get_cru(); + + if (IS_ERR(cru)) + return PTR_ERR(cru); + switch (type) { + case RESET_WARM: + writel(0xeca8, &cru->cru_glb_srst_snd_value); + break; + case RESET_COLD: + writel(0xfdb9, &cru->cru_glb_srst_fst_value); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct reset_ops rk3036_reset = { + .request = rk3036_reset_request, +}; + +U_BOOT_DRIVER(reset_rk3036) = { + .name = "rk3036_reset", + .id = UCLASS_RESET, + .ops = &rk3036_reset, +};