Existing dm code for ahb gate clock will be suitable to handle sun4i,5i,6i and 7i U-Boot specific mmc dt nodes, which are different from Linux in terms of clocks phandle notation.
U-Boot DT clocks phandle follow direct ahb and clock address on node definition with specific bit position, but Linux clocks phandle follow macros to define AHB and MMC clocks so-that the ccu driver will set the bits accordingly.
Clocks phandle notations in U-Boot for higher Allwinner SoC start from sun8i, sun50i are following Linux notation to sync with common node definition along with proper clock driver handling.
So refactor the ahb gate, clock setup to handle all type of Allwinner SoCs. Since we don't have proper CLK driver yet, this code using driver data to differentiate require SoC specific data.
This require existing U-Boot mmc DT nodes need to sync with Linux and the subsequent patches are doing the same.
Cc: Simon Glass sjg@chromium.org Cc: Jaehoon Chung jh80.chung@samsung.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/mmc/sunxi_mmc.c | 39 ++++++++++++++++++++++++++++----------- 1 file changed, 28 insertions(+), 11 deletions(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 7fa1ae8b16..38171b81f3 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -569,8 +569,8 @@ static int sunxi_mmc_probe(struct udevice *dev) struct sunxi_mmc_plat *plat = dev_get_platdata(dev); struct sunxi_mmc_priv *priv = dev_get_priv(dev); struct mmc_config *cfg = &plat->cfg; + struct sunxi_ccm_reg *ccm; struct ofnode_phandle_args args; - u32 *gate_reg; int bus_width, ret;
cfg->name = dev->name; @@ -589,21 +589,38 @@ static int sunxi_mmc_probe(struct udevice *dev) cfg->f_max = 52000000;
priv->reg = (void *)dev_read_addr(dev); + priv->mmc_no = (((uintptr_t)priv->reg / 0x1000) - 0x1C0F);
- /* We don't have a sunxi clock driver so find the clock address here */ ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0, - 1, &args); + 0, &args); if (ret) return ret; - priv->mclkreg = (u32 *)ofnode_get_addr(args.node);
- ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0, - 0, &args); - if (ret) - return ret; - gate_reg = (u32 *)ofnode_get_addr(args.node); - setbits_le32(gate_reg, 1 << args.args[0]); - priv->mmc_no = args.args[0] - 8; + ccm = (struct sunxi_ccm_reg *)ofnode_get_addr(args.node); + if (IS_ERR(ccm)) + return PTR_ERR(ccm); + + /* enable ahb gate */ + setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no))); + + /* find clock reg */ + switch (priv->mmc_no) { + case 0: + priv->mclkreg = &ccm->sd0_clk_cfg; + break; + case 1: + priv->mclkreg = &ccm->sd1_clk_cfg; + break; + case 2: + priv->mclkreg = &ccm->sd2_clk_cfg; + break; + case 3: + priv->mclkreg = &ccm->sd3_clk_cfg; + break; + default: + printf("Wrong mmc number %d\n", priv->mmc_no); + return -EINVAL; + }
ret = mmc_set_mod_clk(priv, 24000000); if (ret)