On Tue, Jan 15, 2019 at 09:20:16AM +0100, Lukasz Majewski wrote:
Hi Tom,
On Mon, Jan 14, 2019 at 03:17:30PM +0100, Lukasz Majewski wrote:
This commit provides update to the bk4r1.dts file with more on SoC HW description. Moreover, a new vf610-pcm052.drsi file has been introduced to reuse the common code between devices based on Phytec's pcm052 modules. Ported from Linux kernel - v4.20 (tag)
Signed-off-by: Lukasz Majewski lukma@denx.de
arch/arm/dts/bk4r1.dts | 108 ++++++++++++----- arch/arm/dts/pcm052.dts | 6 +- arch/arm/dts/vf610-pcm052.dtsi | 266 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 346 insertions(+), 34 deletions(-) create mode 100644 arch/arm/dts/vf610-pcm052.dtsi
diff --git a/arch/arm/dts/bk4r1.dts b/arch/arm/dts/bk4r1.dts index 866b80e0b0..55cd53384a 100644 --- a/arch/arm/dts/bk4r1.dts +++ b/arch/arm/dts/bk4r1.dts @@ -1,47 +1,97 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /*
- (C) Copyright 2018
- Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
*/
- Copyright 2016 Toradex AG
/dts-v1/; -#include "vf.dtsi" +#include "vf610-pcm052.dtsi" +#include "vf610-pinfunc.h"
/ {
- model = "Phytec phyCORE-Vybrid";
- compatible = "phytec,pcm052", "fsl,vf610";
- model = "Liebherr (LVF) BK4 Vybrid Board";
- compatible = "lvf,bk4", "fsl,vf610";
- chosen {
stdout-path = &uart1;- };
- leds {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_gpio_leds>;
- aliases {
spi0 = &qspi0;- };
compatible = "gpio-leds";-};
/* PTE15 PORT3[24] H6 green */led@0 {label = "0";gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;default-state = "off";};/* PTA12 PORT0[5] H5 green */led@1 {label = "1";gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;default-state = "off";};/* PTE20 PORT3[39] H4 green */led@2 {label = "2";gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;default-state = "off";};-&uart1 {
- status = "okay";
/* PTE12 PORT3[21] H3 green */led@3 {label = "3";gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;default-state = "off";};/* LED6 is now PRESET ETH -> PTA16 PORT0[6] H6red */
/* PTE9 PORT3[18] H5 red */led@4 {label = "5";gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;default-state = "off";};/* PTE23 PORT4[0] H4 red */led@5 {label = "6";gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;default-state = "off";};/* PTE16 PORT3[25] H3 red */led@6 {label = "7";gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;default-state = "off";};- };
};
-&qspi0 {
- bus-num = <0>;
- num-cs = <2>;
- status = "okay";
- qflash0: spi_flash@0 {
#address-cells = <1>;#size-cells = <1>;compatible = "spi-flash";spi-max-frequency = <108000000>;reg = <0>;+&iomuxc {
- pinctrl-0 = <&pinctrl_ddr &pinctrl_hog>;
- pinctrl_hog: hoggrp {
fsl,pins = </* ETH control pins */VF610_PAD_PTE17__GPIO_1220x1183
VF610_PAD_PTA16__GPIO_6 0x1183>;
- qflash1: spi_flash@1 {
#address-cells = <1>;#size-cells = <1>;compatible = "spi-flash";spi-max-frequency = <66000000>;reg = <1>;
- pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = </* LEDS */VF610_PAD_PTE15__GPIO_120 0x1183VF610_PAD_PTA12__GPIO_5 0x1183VF610_PAD_PTE9__GPIO_114 0x1183VF610_PAD_PTE20__GPIO_125 0x1183VF610_PAD_PTE23__GPIO_128 0x1183VF610_PAD_PTE16__GPIO_121 0x1183>;}; diff --git a/arch/arm/dts/pcm052.dts b/arch/arm/dts/pcm052.dts index 6489fdc6f4..22026024ea 100644 --- a/arch/arm/dts/pcm052.dts +++ b/arch/arm/dts/pcm052.dts @@ -4,7 +4,7 @@ */
/dts-v1/; -#include "vf.dtsi" +#include "vf610-pcm052.dtsi"
/ { model = "Phytec phyCORE-Vybrid"; @@ -15,7 +15,3 @@ };
};
-&uart1 {
- status = "okay";
-}; diff --git a/arch/arm/dts/vf610-pcm052.dtsi b/arch/arm/dts/vf610-pcm052.dtsi new file mode 100644 index 0000000000..034290526d --- /dev/null +++ b/arch/arm/dts/vf610-pcm052.dtsi @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- (C) Copyright 2018
- Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
- */
+/dts-v1/; +#include "vf.dtsi" +#include "vf610-pinfunc.h"
+/ {
- chosen {
stdout-path = &uart1;- };
- aliases {
spi0 = &qspi0;mmc0 = &esdhc1;- };
+};
+&aips0 {
- u-boot,dm-pre-reloc;
+};
+&esdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_esdhc1>;
- bus-width = <4>;
- cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
- status = "okay";
+};
+&fec0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_eth>;
- phy-mode = "rmii";
- status = "okay";
+};
+&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_eth1>;
- phy-mode = "rmii";
- status = "okay";
+};
+&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
- eeprom: eeprom@50 {
compatible = "atmel,24c256";reg = <0x50>;pagesize = <64>;u-boot,i2c-offset-len = <2>;- };
- m41t62: rtc@68 {
compatible = "st,m41t62";reg = <0x68>;- };
+};
+&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ddr>;
- pinctrl_ddr: ddrgrp {
fsl,pins = <VF610_PAD_DDR_A15__DDR_A_150x1c0
VF610_PAD_DDR_A14__DDR_A_140x1c0
VF610_PAD_DDR_A13__DDR_A_130x1c0
VF610_PAD_DDR_A12__DDR_A_120x1c0
VF610_PAD_DDR_A11__DDR_A_110x1c0
VF610_PAD_DDR_A10__DDR_A_100x1c0
VF610_PAD_DDR_A9__DDR_A_90x1c0
VF610_PAD_DDR_A8__DDR_A_80x1c0
VF610_PAD_DDR_A7__DDR_A_70x1c0
VF610_PAD_DDR_A6__DDR_A_60x1c0
VF610_PAD_DDR_A5__DDR_A_50x1c0
VF610_PAD_DDR_A4__DDR_A_40x1c0
VF610_PAD_DDR_A3__DDR_A_30x1c0
VF610_PAD_DDR_A2__DDR_A_20x1c0
VF610_PAD_DDR_A1__DDR_A_10x1c0
VF610_PAD_DDR_A0__DDR_A_00x1c0
VF610_PAD_DDR_BA2__DDR_BA_20x1c0
VF610_PAD_DDR_BA1__DDR_BA_10x1c0
VF610_PAD_DDR_BA0__DDR_BA_00x1c0
VF610_PAD_DDR_CAS__DDR_CAS_B0x1c0
VF610_PAD_DDR_CKE__DDR_CKE_00x1c0
VF610_PAD_DDR_CLK__DDR_CLK_00x101c0
VF610_PAD_DDR_CS__DDR_CS_B_00x1c0
VF610_PAD_DDR_D15__DDR_D_150x1c0
VF610_PAD_DDR_D14__DDR_D_140x1c0
VF610_PAD_DDR_D13__DDR_D_130x1c0
VF610_PAD_DDR_D12__DDR_D_120x1c0
VF610_PAD_DDR_D11__DDR_D_110x1c0
VF610_PAD_DDR_D10__DDR_D_100x1c0
VF610_PAD_DDR_D9__DDR_D_90x1c0
VF610_PAD_DDR_D8__DDR_D_80x1c0
VF610_PAD_DDR_D7__DDR_D_70x1c0
VF610_PAD_DDR_D6__DDR_D_60x1c0
VF610_PAD_DDR_D5__DDR_D_50x1c0
VF610_PAD_DDR_D4__DDR_D_40x1c0
VF610_PAD_DDR_D3__DDR_D_30x1c0
VF610_PAD_DDR_D2__DDR_D_20x1c0
VF610_PAD_DDR_D1__DDR_D_10x1c0
VF610_PAD_DDR_D0__DDR_D_00x1c0
VF610_PAD_DDR_DQM1__DDR_DQM_10x1c0
VF610_PAD_DDR_DQM0__DDR_DQM_00x1c0
VF610_PAD_DDR_DQS1__DDR_DQS_10x101c0
VF610_PAD_DDR_DQS0__DDR_DQS_00x101c0
VF610_PAD_DDR_RAS__DDR_RAS_B0x1c0
VF610_PAD_DDR_WE__DDR_WE_B0x1c0
VF610_PAD_DDR_ODT1__DDR_ODT_00x1c0
VF610_PAD_DDR_ODT0__DDR_ODT_10x1c0
VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE10x1c0
VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE00x1c0
VF610_PAD_DDR_RESETB0x1006c
>;u-boot,dm-pre-reloc;- };
- pinctrl_esdhc1: esdhc1grp {
fsl,pins = <VF610_PAD_PTA24__ESDHC1_CLK0x31ef
VF610_PAD_PTA25__ESDHC1_CMD0x31ef
VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
VF610_PAD_PTB28__GPIO_980x219d
>;- };
- pinctrl_eth: ethgrp {
fsl,pins = <VF610_PAD_PTA6__RMII_CLKIN0x30dd
VF610_PAD_PTC0__ENET_RMII0_MDC0x30de
VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30dfVF610_PAD_PTC2__ENET_RMII0_CRS0x30dd
VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30ddVF610_PAD_PTC4__ENET_RMII0_RXD0 0x30ddVF610_PAD_PTC5__ENET_RMII0_RXER 0x30ddVF610_PAD_PTC6__ENET_RMII0_TXD1 0x30deVF610_PAD_PTC7__ENET_RMII0_TXD0 0x30deVF610_PAD_PTC8__ENET_RMII0_TXEN 0x30de>;- };
- pinctrl_eth1: eth1grp {
fsl,pins = <VF610_PAD_PTC9__ENET_RMII1_MDC 0x30de
VF610_PAD_PTC10__ENET_RMII1_MDIO0x30df
VF610_PAD_PTC11__ENET_RMII1_CRS0x30dd
VF610_PAD_PTC12__ENET_RMII1_RXD10x30dd
VF610_PAD_PTC13__ENET_RMII1_RXD00x30dd
VF610_PAD_PTC14__ENET_RMII1_RXER0x30dd
VF610_PAD_PTC15__ENET_RMII1_TXD10x30de
VF610_PAD_PTC16__ENET_RMII1_TXD00x30de
VF610_PAD_PTC17__ENET_RMII1_TXEN0x30de
>;- };
- pinctrl_i2c2: i2c2grp {
fsl,pins = <VF610_PAD_PTA22__I2C2_SCL0x34df
VF610_PAD_PTA23__I2C2_SDA0x34df
>;- };
- pinctrl_nfc: nfcgrp {
fsl,pins = <VF610_PAD_PTD31__NF_IO150x28df
VF610_PAD_PTD30__NF_IO140x28df
VF610_PAD_PTD29__NF_IO130x28df
VF610_PAD_PTD28__NF_IO120x28df
VF610_PAD_PTD27__NF_IO110x28df
VF610_PAD_PTD26__NF_IO100x28df
VF610_PAD_PTD25__NF_IO90x28df
VF610_PAD_PTD24__NF_IO80x28df
VF610_PAD_PTD23__NF_IO70x28df
VF610_PAD_PTD22__NF_IO60x28df
VF610_PAD_PTD21__NF_IO50x28df
VF610_PAD_PTD20__NF_IO40x28df
VF610_PAD_PTD19__NF_IO30x28df
VF610_PAD_PTD18__NF_IO20x28df
VF610_PAD_PTD17__NF_IO10x28df
VF610_PAD_PTD16__NF_IO00x28df
VF610_PAD_PTB24__NF_WE_B0x28c2
VF610_PAD_PTB25__NF_CE0_B0x28c2
VF610_PAD_PTB27__NF_RE_B0x28c2
VF610_PAD_PTC26__NF_RB_B0x283d
VF610_PAD_PTC27__NF_ALE0x28c2
VF610_PAD_PTC28__NF_CLE0x28c2
>;- };
- pinctrl_qspi0: qspi0grp {
fsl,pins = <VF610_PAD_PTD0__QSPI0_A_QSCK 0x397fVF610_PAD_PTD1__QSPI0_A_CS0 0x397fVF610_PAD_PTD2__QSPI0_A_DATA3 0x397fVF610_PAD_PTD3__QSPI0_A_DATA2 0x397fVF610_PAD_PTD4__QSPI0_A_DATA1 0x397fVF610_PAD_PTD5__QSPI0_A_DATA0 0x397fVF610_PAD_PTD7__QSPI0_B_QSCK 0x397fVF610_PAD_PTD8__QSPI0_B_CS0 0x397fVF610_PAD_PTD11__QSPI0_B_DATA10x397f
VF610_PAD_PTD12__QSPI0_B_DATA00x397f
>;- };
- pinctrl_uart1: uart1grp {
fsl,pins = <VF610_PAD_PTB4__UART1_TX0x21a2
VF610_PAD_PTB5__UART1_RX0x21a1
>;u-boot,dm-pre-reloc;- };
+};
+&nfc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nfc>;
- status = "okay";
+};
+&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- u-boot,dm-pre-reloc;
- status = "okay";
+};
Any/all u-boot,WHATEVER flags go in the $(basename)-u-boot.dtsi file so that $(basename) can be kept as-is from Linux. Looking things over briefly I suspect we have a higher level issue in that we shouldn't have "pcm052.dts" at all and only "vf610-pcm052.dts" or however it syncs up with what's in Linux.
The problem is that pcm052 is not supported / added to Linux (maybe there are some dts files for it out of tree - I don't know. As of v5.0.-rc2 there weren't any).
Why is it not upstream? What are the plans to push it upstream? But even then, why is it not following the normal naming convention?
The work done in this patch simply extracts the bk4 and pcm052 common DTS code and creates new vf610-pcm052.dtsi file.
OK.
Just a side note - the Vybrid structure of DTS/DTSI files in u-boot differs considerably from the one in Linux (v5.0-rc2). For example in u-boot we do not have vf500.dtsi - the structure (of DTS) is trimmed due to constraints of overall u-boot.vyb size (which was apparent when I ported some common code from Linux to vf.dtsi file).
We should probably get in sync with Linux then, and use the normal mechanism to trim out properties.