Re: [U-Boot] [PATCH 2/6] arm: exynos: Add RPLL for Exynos5420

ping.

On Mon, Sep 30, 2013 at 4:50 PM, Ajay Kumar ajaykumar.rs@samsung.comwrote:

RPLL is needed to drive the LCD panel on Exynos5420 based boards.

Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com

arch/arm/cpu/armv7/exynos/clock_init.h | 3 +++ arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 +++++++++++++ 2 files changed, 16 insertions(+)

diff --git a/arch/arm/cpu/armv7/exynos/clock_init.h b/arch/arm/cpu/armv7/exynos/clock_init.h index a875d0b..fce502f 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init.h +++ b/arch/arm/cpu/armv7/exynos/clock_init.h @@ -75,6 +75,9 @@ struct mem_timings { unsigned spll_mdiv; unsigned spll_pdiv; unsigned spll_sdiv;

•   unsigned rpll_mdiv;
  

•   unsigned rpll_pdiv;
  

•   unsigned rpll_sdiv;
    unsigned pclk_cdrex_ratio;
    unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
  
  

diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c index e7f1496..c91c4a1 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c @@ -179,6 +179,10 @@ struct mem_timings mem_timings[] = { .spll_mdiv = 0xc8, .spll_pdiv = 0x3, .spll_sdiv = 0x2,

•           /* RPLL @266MHz */
  

•           .rpll_mdiv = 0x10A,
  

•           .rpll_pdiv = 0x3,
  

•           .rpll_sdiv = 0x3,
  
            .direct_cmd_msr = {
                    0x00020018, 0x00030000, 0x00010046, 0x00000d70,
  

@@ -800,6 +804,7 @@ static void exynos5420_system_clock_init(void) writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock); writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock); writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);

•   writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock);
  
    setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
  
  

@@ -898,6 +903,14 @@ static void exynos5420_system_clock_init(void) while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0) ;

•   /* Set RPLL */
  

•   writel(RPLL_CON2_VAL, &clk->rpll_con2);
  

•   writel(RPLL_CON1_VAL, &clk->rpll_con1);
  

•   val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv);
  

•   writel(val, &clk->rpll_con0);
  

•   while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0)
  

•           ;
  

•   writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
    writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
  
  

-- 1.7.12.4

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