Re: [U-Boot] [PATCH 1/7] Tegra30: Add AVP (arm720t) files

Hi Tom,

On Tue, Oct 2, 2012 at 3:45 PM, Tom Warren twarren.nvidia@gmail.com wrote:

This provides SPL support for T30 boards - AVP early init, plus CPU (A9) init/jump to main U-Boot.

Signed-off-by: Tom Warren twarren@nvidia.com

arch/arm/cpu/arm720t/tegra-common/cpu.h | 48 +-- arch/arm/cpu/arm720t/tegra-common/spl.c | 3 +- .../arm/cpu/arm720t/tegra30}/Makefile | 20 +- arch/arm/cpu/arm720t/tegra30/config.mk | 19 + arch/arm/cpu/arm720t/tegra30/cpu.c | 516 ++++++++++++++++++++ 5 files changed, 554 insertions(+), 52 deletions(-) copy {board/compal/paz00 => arch/arm/cpu/arm720t/tegra30}/Makefile (68%) create mode 100644 arch/arm/cpu/arm720t/tegra30/config.mk create mode 100644 arch/arm/cpu/arm720t/tegra30/cpu.c

I just have a few additional comments.

diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h b/arch/arm/cpu/arm720t/tegra-common/cpu.h index 6804cd7..0d9a3c2 100644

diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c new file mode 100644 index 0000000..e0821ef --- /dev/null +++ b/arch/arm/cpu/arm720t/tegra30/cpu.c @@ -0,0 +1,516 @@ +/*

• • Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
• • This program is free software; you can redistribute it and/or modify it
• • under the terms and conditions of the GNU General Public License,
• • version 2, as published by the Free Software Foundation.
• • This program is distributed in the hope it will be useful, but WITHOUT
• • ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
• • FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
• • more details.
• • You should have received a copy of the GNU General Public License
• • along with this program. If not, see http://www.gnu.org/licenses/.
• */

+#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/flow.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/clk_rst.h> +#include <asm/arch-tegra/fuse.h> +#include <asm/arch-tegra/pmc.h> +#include <asm/arch-tegra/scu.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include "../tegra-common/cpu.h"

+struct clk_pll_table {

•   u16             n;
  

•   u16             m;
  

•   u8              p;
  

•   u8              cpcon;
  

+};

+/* ~0=uninitialized/unknown, 0=false, 1=true */ +uint32_t is_tegra_processor_reset = 0xffffffff;

+/*

• • Timing tables for each SOC for all four oscillator options.
• */

+static struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_COUNT]

•                                           [CLOCK_OSC_FREQ_COUNT] = {
  

•   /* T20: 1 GHz */
  

•   {{ 1000, 13, 0, 12},    /* OSC 13M */
  

•    { 625,  12, 0, 8},     /* OSC 19.2M */
  

•    { 1000, 12, 0, 12},    /* OSC 12M */
  

•    { 1000, 26, 0, 12},    /* OSC 26M */
  

•   },
  

•   /* T25: 1.2 GHz */
  

•   {{ 923, 10, 0, 12},
  

•    { 750, 12, 0, 8},
  

•    { 600,  6, 0, 12},
  

•    { 600, 13, 0, 12},
  

•   },
  

•   /* T30(slow): 1.0 GHz */
  

•   {{ 1000,  13, 0, 8},
  

•    { 625,  12, 0, 4},
  

•    { 1000, 12, 0, 8},
  

•    { 1000,  26, 0, 8},
  

•   },
  

•   /* T30(high): 1.4 GHz */
  

•   {{ 862, 8, 0, 8},
  

•    { 583, 8, 0, 4},
  

•    { 700, 6, 0, 8},
  

•    { 700, 13, 0, 8},
  

•   },
  

•   /* TEGRA_SOC2_SLOW: 312 MHz */
  

•   {{ 312, 13, 0, 12},     /* OSC 13M */
  

•    { 260, 16, 0, 8},      /* OSC 19.2M */
  

•    { 312, 12, 0, 12},     /* OSC 12M */
  

•    { 312, 26, 0, 12},     /* OSC 26M */
  

•   },
  

+};

+enum tegra_family_t {

•   TEGRA_FAMILY_T2x,
  

•   TEGRA_FAMILY_T3x,
  

+};

This is fine here since the function that uses it is static. I wonder if we want to export that function one day?

+static int get_chip_type(void) +{

•   /*
  

•    * T30 has two options. We will return TEGRA_SOC_T30 until
  

•    * we have the fdt set up when it may change to
  

•    * TEGRA_SOC_T30_408MHZ depending on what we set PLLP to.
  

•    */
  

•   if (clock_get_rate(CLOCK_ID_PERIPH) == 408000000)
  

•           return TEGRA_SOC_T30_408MHZ;
  

•   else
  

•           return TEGRA_SOC_T30;
  

+}

+static enum tegra_family_t get_family(void) +{

•   u32 reg, chip_id;
  

•   debug("tegra_get_family entry\n");
  

•   reg = readl(NV_PA_APB_MISC_BASE + GP_HIDREV);
  

•   chip_id = reg >> 8;
  

•   chip_id &= 0xff;
  

•   debug("  tegra_get_family: chip_id = %x\n", chip_id);
  

•   if (chip_id == 0x30)
  

•           return TEGRA_FAMILY_T3x;
  

•   else
  

•           return TEGRA_FAMILY_T2x;
  

+}

+int get_num_cpus(void) +{

•   return get_family() == TEGRA_FAMILY_T3x ? 4 : 2;
  

+}

+static void adjust_pllp_out_freqs(void) +{

•   struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  

•   struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
  

•   u32 reg;
  

•   /* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
  

•   reg = readl(&pll->pll_out[0]);     /* OUTA, contains OUT2 / OUT1 */
  

•   reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
  

•           | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
  

•   writel(reg, &pll->pll_out[0]);
  

•   reg = readl(&pll->pll_out[1]);   /* OUTB, contains OUT4 / OUT3 */
  

•   reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
  

•           | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
  

•   writel(reg, &pll->pll_out[1]);
  

+}

+static int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,

•           u32 divp, u32 cpcon)
  

From this function on I see quite a bit of similarity with the tegra20

version. IMO the number of cpus can just be the result of get_num_cpus(), most of the clocks are the same, and differences can either be in this file or behind a conditional check for the family. Otherwise we have duplicated code here.

Regards, Simon