cmd/mmc.c
Maybe SD controller on some vendor platforms doesn't support SNOOP. flush_cache() is required to sync between DDR and cache. Should be careful to remove this.
-----Original Message----- From: Qiang Zhao Sent: Wednesday, August 23, 2017 11:14 AM To: Y.b. Lu; York Sun; Bin Meng; Grygorii Strashko; Michal Simek; Angelo Dureghello; Kever Yang; Jaehoon Chung; Albert Aribaud; Marcel Ziswiler; Markus Niebel; Z.q. Hou; Sumit Garg; Joe Hershberger; Stefan Roese; Wenbin Song; Simon Glass; Max Krummenacher; Masahiro Yamada; Tomas Melin; Q.y. Gong; Tom Rini; U-Boot Mailing List Subject: RE: [PATCH] blk: Remove various places that do flush cache after read
+Yangbo
Best Regards Qiang Zhao
-----Original Message----- From: York Sun Sent: Wednesday, August 23, 2017 12:49 AM To: Bin Meng bmeng.cn@gmail.com; Grygorii Strashko grygorii.strashko@ti.com; Michal Simek michal.simek@xilinx.com; Angelo Dureghello angelo@sysam.it; Kever Yang kever.yang@rock-chips.com; Jaehoon Chung jh80.chung@samsung.com; Albert Aribaud albert.u.boot@aribaud.net; Marcel Ziswiler marcel.ziswiler@toradex.com; Markus Niebel Markus.Niebel@tq-group.com; Z.q. Hou zhiqiang.hou@nxp.com; Sumit Garg sumit.garg@nxp.com; Joe Hershberger joe.hershberger@ni.com; Stefan Roese sr@denx.de; Wenbin Song wenbin.song@nxp.com; Qiang Zhao qiang.zhao@nxp.com; Simon Glass sjg@chromium.org; Max Krummenacher max.krummenacher@toradex.com; Masahiro Yamada yamada.masahiro@socionext.com; Tomas Melin tomas.melin@vaisala.com; Q.y. Gong qianyu.gong@nxp.com; Tom Rini trini@konsulko.com; U-Boot Mailing List u-boot@lists.denx.de Subject: Re: [PATCH] blk: Remove various places that do flush cache after read
On 08/21/2017 08:42 PM, Bin Meng wrote:
All these places seem to inherit the codes from the MMC driver where a FIXME was put in the comment. However the correct operation after read should be cache invalidate, not flush.
The underlying drivers should be responsible for the cache operation. Remove these codes completely.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/arm/cpu/armv8/fsl-layerscape/ppa.c | 15 --------------- board/toradex/common/tdx-cfg-block.c | 2 -- cmd/mmc.c | 2 -- drivers/block/blk-uclass.c | 3 --- drivers/block/blk_legacy.c | 3 --- drivers/net/fm/fm.c | 2 -- drivers/net/phy/cortina.c | 2 -- drivers/qe/qe.c | 2 -- 8 files changed, 31 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c index 24ddb5d..bbf8bba 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c @@ -107,9 +107,6 @@ int ppa_init(void) return -EIO; }
- /* flush cache after read */
- flush_cache((ulong)fitp, cnt * 512);
NACK here.
ret = fdt_check_header(fitp); if (ret) { free(fitp); @@ -134,9 +131,6 @@ int ppa_init(void) } debug("Read PPA header to 0x%p\n", ppa_hdr_ddr);
- /* flush cache after read */
- flush_cache((ulong)ppa_hdr_ddr, cnt * 512);
- ppa_esbc_hdr = (uintptr_t)ppa_hdr_ddr; #endif
@@ -164,9 +158,6 @@ int ppa_init(void) return -EIO; }
- /* flush cache after read */
- flush_cache((ulong)ppa_fit_addr, cnt * 512);
- #elif defined(CONFIG_SYS_LS_PPA_FW_IN_NAND) struct fdt_header fit;
@@ -208,9 +199,6 @@ int ppa_init(void) } debug("Read PPA header to 0x%p\n", ppa_hdr_ddr);
- /* flush cache after read */
- flush_cache((ulong)ppa_hdr_ddr, fw_length);
- ppa_esbc_hdr = (uintptr_t)ppa_hdr_ddr; #endif
@@ -232,9 +220,6 @@ int ppa_init(void) CONFIG_SYS_LS_PPA_FW_ADDR); return -EIO; }
- /* flush cache after read */
- flush_cache((ulong)ppa_fit_addr, fw_length); #else #error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined" #endif
Hold on for ppa.c. We need to flush the cache after reading PPA image and it header after loading. These images need to be flushed into main memory. I will need to confirm with our team if we can remove flushing
here.
York