On Feb 1, 2011, at 1:46 PM, Haiying Wang wrote:
On Tue, 2011-02-01 at 13:15 -0600, Kumar Gala wrote:
On Feb 1, 2011, at 11:01 AM, Haiying Wang wrote:
On Tue, 2011-02-01 at 10:50 -0600, Scott Wood wrote:
If it is a one time setting, there should be no problem to put it into board code. But these pin settings need to be done before any usage of phy read/write (accessing MDIO/MDC), and need to be released after the usage of phy, thus the devices connected to eLBC like NAND flash/BCSR can be accessed. If we use board code to set/release the pin, we don't know when the phy access and nand flash access will happen.
Is this actually a board issue or an SoC issue?
It is not a board issue. It is a SoC *feature*. Too many pins are muxed on P1021. For this case, LBCTL of eLBC is muxed with QE's CE_PB[20] which is used for MDIO signal.
Haiying
But its a board decision on how they want to utilize those pins and for what feature.
Yes, you can say that. If the board doesn't have QE UCC ETH support at all, we won't have to add such code in QE driver. But if there is QE UCC ETH on board, we have no choice to decide which pins to use. We definitely need to use CE_PB[20] for MDIO signal, there is no other GPIO pins to use for QE's MDIO.
Haiying
If that case and controlled by some CONFIG_QE_* define than we clearly can make the choice in non-board specific code.
- k