Marcel,
-----Original Message----- From: Marcel Ziswiler [mailto:marcel@ziswiler.com] Sent: Wednesday, August 05, 2015 7:37 AM To: u-boot@lists.denx.de Cc: Tom Warren; Tom Warren; Albert Aribaud; Tom Rini; Thierry Reding; Simon Glass; Stephen Warren; Masahiro Yamada; Marcel Ziswiler Subject: [PATCH] tegra: pll: fix pllx cpcon in pllinfo table for t20/t30
From: Marcel Ziswiler marcel.ziswiler@toradex.com
Fix CPCON mask and shift of PLLX for T20 as well as T30. While the former's PLLX did not even lock any more resulting is super slow operation the later seemed to still lock OK. Nonetheless I this patch fixes it for both.
Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com
Note: This patch requires Tom's two Tegra PLL patches being applied first.
Do you mind if I just roll this into my pllinfo patch when I apply it to u-boot-tegra/master and send the PR? I'll be sure to credit your work!
Tom -- nvpublic
arch/arm/mach-tegra/tegra20/clock.c | 2 +- arch/arm/mach- tegra/tegra30/clock.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach- tegra/tegra20/clock.c index df9f412..dea459b 100644 --- a/arch/arm/mach-tegra/tegra20/clock.c +++ b/arch/arm/mach-tegra/tegra20/clock.c @@ -379,7 +379,7 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */ { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F,
.lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0,.kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */
.lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF,.kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */ { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c index 4267bb2..3ce508b 100644 --- a/arch/arm/mach-tegra/tegra30/clock.c +++ b/arch/arm/mach-tegra/tegra30/clock.c @@ -428,7 +428,7 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */ { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
.lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0,.kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */
.lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF,.kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */ { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, -- 2.4.3