Add the TPM device found on the GW71xx revision E PCB.
This hangs off of SPI2, uses gpio1_10 as a CS and gpio1_11 as RST#.
Signed-off-by: Tim Harvey tharvey@gateworks.com --- arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi | 9 +++++++++ arch/arm/dts/imx8mp-venice-gw71xx.dtsi | 10 +++++++++- 2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi index 5c33f8c9cdcf..216a7a0d8d7c 100644 --- a/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi @@ -4,6 +4,15 @@ */ #include "imx8mp-venice-gw702x-u-boot.dtsi"
+&gpio1 { + tpm_rst { + gpio-hog; + output-high; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "tpm_rst#"; + }; +}; + &gpio4 { dio_1 { gpio-hog; diff --git a/arch/arm/dts/imx8mp-venice-gw71xx.dtsi b/arch/arm/dts/imx8mp-venice-gw71xx.dtsi index 86999f52d4b2..4b1dbaa64b6b 100644 --- a/arch/arm/dts/imx8mp-venice-gw71xx.dtsi +++ b/arch/arm/dts/imx8mp-venice-gw71xx.dtsi @@ -48,8 +48,15 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio1 10 GPIO_ACTIVE_LOW>; status = "okay"; + + tpm@1 { + compatible = "tcg,tpm_tis-spi"; + reg = <0x1>; + spi-max-frequency = <36000000>; + }; };
&gpio4 { @@ -217,6 +224,7 @@ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + MX8MP_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 >; };