Enable use of the instruction cache immediately after it has been initialised. This will only take effect if U-Boot was linked to run from kseg0 rather than kseg1, but when this is the case the data cache initialisation code will run cached & thus significantly faster.
Signed-off-by: Paul Burton paul.burton@imgtec.com ---
Changes in v3: None Changes in v2: None
arch/mips/cpu/start.S | 8 -------- arch/mips/lib/cache_init.S | 13 +++++++++++++ 2 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index fc6dd66..827a544 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -12,10 +12,6 @@ #include <asm/regdef.h> #include <asm/mipsregs.h>
-#ifndef CONFIG_SYS_MIPS_CACHE_MODE -#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT -#endif - #ifndef CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ CONFIG_SYS_INIT_SP_OFFSET) @@ -154,10 +150,6 @@ reset: PTR_LA t9, mips_cache_reset jalr t9 nop - - /* ... and enable them */ - li t0, CONFIG_SYS_MIPS_CACHE_MODE - mtc0 t0, CP0_CONFIG #endif
/* Set up temporary stack */ diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index bc8ab27..974dfe9 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -172,6 +172,19 @@ LEAF(mips_cache_reset) cache_loop t0, t1, t8, INDEX_STORE_TAG_I #endif
+ /* Enable use of the I-cache by setting Config.K0 */ + sync + mfc0 t0, CP0_CONFIG + li t1, CONFIG_SYS_MIPS_CACHE_MODE +#if __mips_isa_rev >= 2 + ins t0, t1, 0, 3 +#else + ori t0, t0, CONF_CM_CMASK + xori t0, t0, CONF_CM_CMASK + or t0, t0, t1 +#endif + mtc0 t0, CP0_CONFIG + /* * then initialize D-cache. */