From: Saeed Nowshadi saeed.nowshadi@xilinx.com
Align clock output names with node references.
Signed-off-by: Saeed Nowshadi saeed.nowshadi@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index bf982e221830..c260411d7571 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019 - 2020, Xilinx, Inc. * * Michal Simek michal.simek@xilinx.com */ @@ -421,14 +421,14 @@ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; - clock-output-names = "si570_hsdp_clk"; + clock-output-names = "si570_zsfp_clk"; }; }; i2c@6 { /* USER_SI570_1 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; - si570_user1_clk: clock-generator@5d { /* u205 */ + si570_user1: clock-generator@5d { /* u205 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5f>; @@ -510,7 +510,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - si570_ddr_dimm2: clock-generator@60 { /* u3 */ + si570_lpddr4clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; @@ -524,7 +524,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <5>; - si570_lpddr4: clock-generator@60 { /* u4 */ + si570_lpddr4clk1: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>;