Enable all cache ways from u-boot proper.
Signed-off-by: Pragnesh Patel pragnesh.patel@sifive.com --- arch/riscv/fu540/Makefile | 3 +- arch/riscv/fu540/cache.c | 58 +++++++++++++++++++++ arch/riscv/include/asm/arch-generic/cache.h | 14 +++++ board/sifive/fu540/fu540.c | 10 +++- 4 files changed, 81 insertions(+), 4 deletions(-) create mode 100644 arch/riscv/fu540/cache.c create mode 100644 arch/riscv/include/asm/arch-generic/cache.h
diff --git a/arch/riscv/fu540/Makefile b/arch/riscv/fu540/Makefile index e3b40ae7d4..3f385e8529 100644 --- a/arch/riscv/fu540/Makefile +++ b/arch/riscv/fu540/Makefile @@ -6,6 +6,5 @@ ifeq ($(CONFIG_SPL_BUILD),y) obj-$(CONFIG_TARGET_SIFIVE_FU540) += spl.o else -# necessary to create built-in.o -obj- += __dummy__.o +obj-y += cache.o endif diff --git a/arch/riscv/fu540/cache.c b/arch/riscv/fu540/cache.c new file mode 100644 index 0000000000..3eb71a06d4 --- /dev/null +++ b/arch/riscv/fu540/cache.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 SiFive, Inc + * + * Authors: + * Pragnesh Patel pragnesh.patel@sifive.com + */ + +#include <common.h> +#include <asm/io.h> +#include <linux/bitops.h> + +#ifdef CONFIG_TARGET_SIFIVE_FU540 +/* Register offsets */ +#define CACHE_CONFIG 0x000 +#define CACHE_ENABLE 0x008 + +#define MASK_NUM_WAYS GENMASK(15, 8) +#define NUM_WAYS_SHIFT 8 +#endif + +DECLARE_GLOBAL_DATA_PTR; + +int cache_enable_ways(void) +{ + const void *blob = gd->fdt_blob; + int node = (-FDT_ERR_NOTFOUND); + fdt_addr_t base; + u32 config; + u32 ways; + + volatile u32 *enable; + +#ifdef CONFIG_TARGET_SIFIVE_FU540 + node = fdt_node_offset_by_compatible(blob, -1, + "sifive,fu540-c000-ccache"); + + if (node < 0) + return node; + + base = fdtdec_get_addr(blob, node, "reg"); + if (base == FDT_ADDR_T_NONE) + return FDT_ADDR_T_NONE; + + config = readl((volatile u32 *)base + CACHE_CONFIG); + ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT; + + enable = (volatile u32 *)(base + CACHE_ENABLE); + + /* memory barrier */ + mb(); + (*enable) = ways - 1; + /* memory barrier */ + mb(); +#endif /* CONFIG_TARGET_SIFIVE_FU540 */ + + return 0; +} diff --git a/arch/riscv/include/asm/arch-generic/cache.h b/arch/riscv/include/asm/arch-generic/cache.h new file mode 100644 index 0000000000..135a17c679 --- /dev/null +++ b/arch/riscv/include/asm/arch-generic/cache.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 SiFive, Inc. + * + * Authors: + * Pragnesh Patel pragnesh.patel@sifve.com + */ + +#ifndef _CACHE_SIFIVE_H +#define _CACHE_SIFIVE_H + +int cache_enable_ways(void); + +#endif /* _CACHE_SIFIVE_H */ diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c index d05529a86b..131fee8898 100644 --- a/board/sifive/fu540/fu540.c +++ b/board/sifive/fu540/fu540.c @@ -12,6 +12,7 @@ #include <linux/io.h> #include <misc.h> #include <spl.h> +#include <asm/arch/cache.h>
/* * This define is a value used for error/unknown serial. @@ -111,8 +112,13 @@ int misc_init_r(void)
int board_init(void) { - /* For now nothing to do here. */ - + int ret; + /* enable all cache ways */ + ret = cache_enable_ways(); + if (ret) { + debug("%s: could not enable cache ways\n", __func__); + return ret; + } return 0; }