From: Bryan Wu pengw@nvidia.com
On Tegra114 and Tegra124 platforms, certain display-related registers cannot be accessed unless the VPR registers are programmed. For bootloader, we probably don't care about VPR, so we disable it (which counts as programming it, and allows those display-related registers to be accessed.
This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c in Chromium OS U-Boot project.
Signed-off-by: Andrew Chew achew@nvidia.com Signed-off-by: Jimmy Zhang jimmzhang@nvidia.com Signed-off-by: Bryan Wu pengw@nvidia.com [acourbot: ensure write went through, vpr.c style changes] Signed-off-by: Alexandre Courbot acourbot@nvidia.com Cc: Tom Warren TWarren@nvidia.com Cc: Stephen Warren swarren@nvidia.com Cc: Terje Bergstrom tbergstrom@nvidia.com --- Changes since v1: - Use proper defines for fields values - Move MC layout to T124 arch as it is exclusive to it - Only compile VPR support if T124 is enabled
arch/arm/cpu/tegra-common/Makefile | 1 + arch/arm/cpu/tegra-common/ap.c | 3 ++ arch/arm/cpu/tegra-common/vpr.c | 45 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-tegra/ap.h | 9 ++++++ arch/arm/include/asm/arch-tegra124/mc.h | 49 +++++++++++++++++++++++++++++++++ 5 files changed, 107 insertions(+) create mode 100644 arch/arm/cpu/tegra-common/vpr.c create mode 100644 arch/arm/include/asm/arch-tegra124/mc.h
diff --git a/arch/arm/cpu/tegra-common/Makefile b/arch/arm/cpu/tegra-common/Makefile index 892556e64451..a18c318739fa 100644 --- a/arch/arm/cpu/tegra-common/Makefile +++ b/arch/arm/cpu/tegra-common/Makefile @@ -14,3 +14,4 @@ obj-y += clock.o obj-y += lowlevel_init.o obj-y += pinmux-common.o obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o +obj-$(CONFIG_TEGRA124) += vpr.o diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c index 91d70da65661..a17dfd1e225e 100644 --- a/arch/arm/cpu/tegra-common/ap.c +++ b/arch/arm/cpu/tegra-common/ap.c @@ -163,4 +163,7 @@ void s_init(void)
/* init the cache */ config_cache(); + + /* init vpr */ + config_vpr(); } diff --git a/arch/arm/cpu/tegra-common/vpr.c b/arch/arm/cpu/tegra-common/vpr.c new file mode 100644 index 000000000000..1a442d9a40ef --- /dev/null +++ b/arch/arm/cpu/tegra-common/vpr.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +/* Tegra vpr routines */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/gp_padctrl.h> +#include <asm/arch/tegra.h> +#include <asm/arch/mc.h> +#include <asm/arch-tegra/ap.h> + +/* Configures VPR. Right now, all we do is turn it off. */ +void config_vpr(void) +{ + struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; + + /* VPR is only in T114 and T124 */ + switch (tegra_get_chip()) { + case CHIPID_TEGRA114: + case CHIPID_TEGRA124: + /* Turn off VPR */ + writel(0, &mc->mc_video_protect_size_mb); + writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED, + &mc->mc_video_protect_reg_ctrl); + /* read back to ensure the write went through */ + readl(&mc->mc_video_protect_reg_ctrl); + break; + default: + break; + } +} diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h index bc5851c1d045..5c8be94d9772 100644 --- a/arch/arm/include/asm/arch-tegra/ap.h +++ b/arch/arm/include/asm/arch-tegra/ap.h @@ -65,3 +65,12 @@ int tegra_get_sku_info(void);
/* Do any chip-specific cache config */ void config_cache(void); + +#if defined(CONFIG_TEGRA124) +/* Do chip-specific vpr config */ +void config_vpr(void); +#else +static inline void config_vpr(void) +{ +} +#endif diff --git a/arch/arm/include/asm/arch-tegra124/mc.h b/arch/arm/include/asm/arch-tegra124/mc.h new file mode 100644 index 000000000000..d526dfe15c30 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/mc.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +#ifndef _TEGRA124_MC_H_ +#define _TEGRA124_MC_H_ + +/** + * Defines the memory controller registers we need/care about + */ +struct mc_ctlr { + u32 reserved0[4]; /* offset 0x00 - 0x0C */ + u32 mc_smmu_config; /* offset 0x10 */ + u32 mc_smmu_tlb_config; /* offset 0x14 */ + u32 mc_smmu_ptc_config; /* offset 0x18 */ + u32 mc_smmu_ptb_asid; /* offset 0x1C */ + u32 mc_smmu_ptb_data; /* offset 0x20 */ + u32 reserved1[3]; /* offset 0x24 - 0x2C */ + u32 mc_smmu_tlb_flush; /* offset 0x30 */ + u32 mc_smmu_ptc_flush; /* offset 0x34 */ + u32 reserved2[6]; /* offset 0x38 - 0x4C */ + u32 mc_emem_cfg; /* offset 0x50 */ + u32 mc_emem_adr_cfg; /* offset 0x54 */ + u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ + u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ + u32 reserved3[12]; /* offset 0x60 - 0x8C */ + u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ + u32 reserved4[338]; /* offset 0x100 - 0x644 */ + u32 mc_video_protect_bom; /* offset 0x648 */ + u32 mc_video_protect_size_mb; /* offset 0x64c */ + u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ +}; + +#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0) +#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0) + +#endif /* _TEGRA124_MC_H_ */