RE: [PATCH 2/2] [RFC] clk: stm32mp1: Handle SoC speed grade configs

Dear Marek,

From: Marek Vasut marex@denx.de Sent: mardi 12 mai 2020 19:07

There are two speed grades of the STM32MP1, the A/C and D/F, the former can run up to 650 MHz, the later at up to 800 MHz. Allow specifying PLL config for both in the DT, so that it is possible to cater for boards which can be populated with either SoC.

Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com

---

drivers/clk/clk_stm32mp1.c | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 50df8425bf..cecc06638e 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -4,6 +4,7 @@ */

#include <common.h> +#include <asm/arch/sys_proto.h> #include <clk-uclass.h> #include <div64.h> #include <dm.h> @@ -1464,6 +1465,12 @@ static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg) setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL); }

+static __maybe_unused int stm32mp1_is_df(void) {

• /* ID bit 7 is set on 15x{D,F}xx and not on 15x{A,C}xx */
• return get_cpu_type() & BIT(7);

+}

static __maybe_unused int pll_set_rate(struct udevice *dev, int pll_id, int div_id, @@ -1491,8 +1498,13 @@ static __maybe_unused int pll_set_rate(struct udevice *dev,

ret = ofnode_read_u32_array(plloff, "cfg", pllcfg, PLLCFG_NB);

• if (ret < 0)

• return -FDT_ERR_NOTFOUND;
  

• if (ret < 0) {

• ret = ofnode_read_u32_array(plloff,
  

• 		stm32mp1_is_df() ? "cfg-df" : "cfg-ac",
  

• 		pllcfg, PLLCFG_NB);
  

• if (ret < 0)
  

• 	return -FDT_ERR_NOTFOUND;
  

• }

  fck_ref = pll_get_fref_ck(priv, pll_id);

@@ -1687,8 +1699,13 @@ static int stm32mp1_clktree(struct udevice *dev) ret = ofnode_read_u32_array(plloff[i], "cfg", pllcfg[i], PLLCFG_NB); if (ret < 0) {

• 	debug("field cfg invalid: error %d\n", ret);
  

• 	return -FDT_ERR_NOTFOUND;
  

• 	ret = ofnode_read_u32_array(plloff[i],
  

• 			stm32mp1_is_df() ? "cfg-df" : "cfg-ac",
  

• 			pllcfg[i], PLLCFG_NB);
  

• 	if (ret < 0) {
  

• 		debug("field cfg invalid: error %d\n", ret);
  

• 		return -FDT_ERR_NOTFOUND;
  

• 	}
  

  } }

@@ -1783,6 +1800,11 @@ static int stm32mp1_clktree(struct udevice *dev) continue;

fracv = ofnode_read_u32_default(plloff[i], "frac", 0);

• if (!fracv) {
  

• 	fracv = ofnode_read_u32_default(plloff[i],
  

• 			stm32mp1_is_df() ? "frac-df" : "frac-ac",
  

• 			0);
  

• }
  

  pll_config(priv, i, pllcfg[i], fracv); ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB); if (!ret) {

-- 2.25.1

The 2 speed grade will be supported with OPP information and HW support,present in kernel device tree (upstream in progress)

I port this patch in U-Boot with: http://patchwork.ozlabs.org/project/uboot/patch/20200421171123.2.Id3620aec4d...

Please check the full serie stm32mp1: use OPP information for PLL1 settings in SPL http://patchwork.ozlabs.org/project/uboot/list/?series=171767

PLL1 settings are now computed in SPL and no more read from DT.

Regards

Patrick