On 2023/7/23 22:55, Jonas Karlman wrote:
The Pine64 SOQuartz Blade board is a carrier board for the SOQuartz CM4-compatible compute module. It features PoE, an M.2 slot, an SD card slot, HDMI, USB, serial and ethernet.
Features tested with a SOQuartz 4GB v1.1 2022-07-11:
- SD-card boot
- eMMC boot
- PCIe/NVMe
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/Makefile | 1 + .../arm/dts/rk3566-soquartz-blade-u-boot.dtsi | 3 + arch/arm/dts/rk3566-soquartz-blade.dts | 194 ++++++++++++++++++ board/pine64/quartz64_rk3566/MAINTAINERS | 3 + configs/soquartz-blade-rk3566_defconfig | 90 ++++++++ doc/board/rockchip/rockchip.rst | 1 + 6 files changed, 292 insertions(+) create mode 100644 arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz-blade.dts create mode 100644 configs/soquartz-blade-rk3566_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index aca2ec44a888..7a41675ef89d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -170,6 +170,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-quartz64-a.dtb \ rk3566-quartz64-b.dtb \ rk3566-radxa-cm3-io.dtb \
- rk3566-soquartz-blade.dtb \ rk3566-soquartz-model-a.dtb \ rk3568-evb.dtb \ rk3568-odroid-m1.dtb \
diff --git a/arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi b/arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi new file mode 100644 index 000000000000..0e662eafa4c7 --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0+
+#include "rk3566-soquartz-u-boot.dtsi" diff --git a/arch/arm/dts/rk3566-soquartz-blade.dts b/arch/arm/dts/rk3566-soquartz-blade.dts new file mode 100644 index 000000000000..4e49bebf548b --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz-blade.dts @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566-soquartz.dtsi"
+/ {
- model = "PINE64 RK3566 SOQuartz on Blade carrier board";
- compatible = "pine64,soquartz-blade", "pine64,soquartz", "rockchip,rk3566";
- /* labeled VCC3V0_SD in schematic to not conflict with PMIC regulator */
- vcc3v0_sd: vcc3v0-sd-regulator {
compatible = "regulator-fixed";regulator-name = "vcc3v0_sd";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;vin-supply = <&vcc3v3_sys>;- };
- /* labeled VCC_SSD in schematic */
- vcc3v3_pcie_p: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";regulator-name = "vcc3v3_pcie_p";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;vin-supply = <&vbus>;- };
- vcc5v_dcin: vcc5v-dcin-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v_dcin";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;- };
+};
+&combphy2 {
- phy-supply = <&vcc3v3_sys>;
- status = "okay";
+};
+&gmac1 {
- status = "okay";
+};
+/*
- i2c1 is exposed on CM1 / Module1A
- pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
- pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
- */
+&i2c1 {
- status = "okay";
+};
+/*
- i2c2 is exposed on CM1 / Module1A - to PI40
- pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
- pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
- */
+&i2c2 {
- status = "disabled";
+};
+/*
- i2c3 is exposed on CM1 / Module1A - to PI40
- pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
- pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
- */
+&i2c3 {
- status = "disabled";
+};
+/*
- i2c4 is exposed on CM2 / Module1B - to PI40
- pin 45 - GPIO24 - i2c4_scl_m1
- pin 47 - GPIO23 - i2c4_sda_m1
- */
+&i2c4 {
- status = "disabled";
+};
+/*
- i2s1_8ch is exposed on CM1 / Module1A - to PI40
- pin 24 - GPIO26 - i2s1_sdi1_m1
- pin 25 - GPIO21 - i2s1_sdo0_m1
- pin 26 - GPIO19 - i2s1_lrck_tx_m1
- pin 27 - GPIO20 - i2s1_sdi0_m1
- pin 29 - GPIO16 - i2s1_sdi3_m1
- pin 30 - GPIO6 - i2s1_sdi2_m1
- pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3
- pin 41 - GPIO25 - i2s1_sdo2_m1
- pin 49 - GPIO18 - i2s1_sclk_tx_m1
- pin 50 - GPIO17 - i2s1_mclk_m1
- pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2
- */
+&i2s1_8ch {
- status = "disabled";
+};
+&led_diy {
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_DISK_ACTIVITY;
- linux,default-trigger = "disk-activity";
- status = "okay";
+};
+&led_work {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- linux,default-trigger = "heartbeat";
- status = "okay";
+};
+&pcie2x1 {
- vpcie3v3-supply = <&vcc3v3_pcie_p>;
- status = "okay";
+};
+&rgmii_phy1 {
- status = "okay";
+};
+/*
- saradc is exposed on CM1 / Module1A - to J2
- pin 94 - AIN1 - saradc_vin3
- pin 96 - AIN0 - saradc_vin2
- */
+&saradc {
- status = "disabled";
+};
+&sdmmc0 {
- vmmc-supply = <&vcc3v0_sd>;
- status = "okay";
+};
+/*
- spi3 is exposed on CM1 / Module1A - to PI40
- pin 37 - GPIO7 - spi3_cs1_m0
- pin 38 - GPIO11 - spi3_clk_m0
- pin 39 - GPIO8 - spi3_cs0_m0
- pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch
- pin 44 - GPIO10 - spi3_mosi_m0
- */
+&spi3 {
- status = "disabled";
+};
+/*
- uart2 is exposed on CM1 / Module1A - to PI40
- pin 51 - GPIO15 - uart2_rx_m0
- pin 55 - GPIO14 - uart2_tx_m0
- */
+&uart2 {
- status = "okay";
+};
+/*
- uart7 is exposed on CM1 / Module1A - to PI40
- pin 46 - GPIO22 - uart7_tx_m2
- pin 47 - GPIO23 - uart7_rx_m2
- */
+&uart7 {
- status = "okay";
+};
+&usb2phy0 {
- status = "okay";
+};
+&usb2phy0_otg {
- phy-supply = <&vbus>;
- status = "okay";
+};
+&usb_host0_xhci {
- status = "okay";
+};
+&vbus {
- vin-supply = <&vcc5v_dcin>;
+}; diff --git a/board/pine64/quartz64_rk3566/MAINTAINERS b/board/pine64/quartz64_rk3566/MAINTAINERS index 748ff5033d93..603d2ee9d5e9 100644 --- a/board/pine64/quartz64_rk3566/MAINTAINERS +++ b/board/pine64/quartz64_rk3566/MAINTAINERS @@ -6,6 +6,7 @@ F: board/pine64/quartz64_rk3566/ F: include/configs/quartz64_rk3566.h F: configs/quartz64-a-rk3566_defconfig F: configs/quartz64-b-rk3566_defconfig +F: configs/soquartz-blade-rk3566_defconfig F: configs/soquartz-model-a-rk3566_defconfig F: arch/arm/dts/rk3566-quartz64-a.dts F: arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi @@ -13,5 +14,7 @@ F: arch/arm/dts/rk3566-quartz64-b.dts F: arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi F: arch/arm/dts/rk3566-soquartz.dtsi F: arch/arm/dts/rk3566-soquartz-u-boot.dtsi +F: arch/arm/dts/rk3566-soquartz-blade.dts +F: arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi F: arch/arm/dts/rk3566-soquartz-model-a.dts F: arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi diff --git a/configs/soquartz-blade-rk3566_defconfig b/configs/soquartz-blade-rk3566_defconfig new file mode 100644 index 000000000000..181c284e73e9 --- /dev/null +++ b/configs/soquartz-blade-rk3566_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-blade" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_QUARTZ64_RK3566=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-blade.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_CLK=y +CONFIG_GPIO_HOG=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index a17bcb2afc1a..254a68b43eaf 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -98,6 +98,7 @@ List of mainline supported Rockchip boards: - Hardkernel ODROID-M1 (odroid-m1-rk3568) - Pine64 Quartz64-A Board (quartz64-a-rk3566_defconfig) - Pine64 Quartz64-B Board (quartz64-b-rk3566_defconfig)
- Pine64 SOQuartz on Blade (soquartz-blade-rk3566_defconfig) - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566_defconfig)
- rk3588