Re: [U-Boot] [PATCH 4/4] fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave

16 Dec 2009


      On Dec 16, 2009, at 10:24 AM, Kumar Gala wrote:
...
From: Dave Liu daveliu@freescale.com
In chip-select interleaving case, we also need set the ODT_RD_CFG
and ODT_WR_CFG in cs1_config register.
Signed-off-by: Dave Liu daveliu@freescale.com
cpu/mpc8xxx/ddr/ctrl_regs.c |    3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
applied to 85xx
- k