Hi Dinh Nguyen,
On Fri, Jun 8, 2012 at 10:26 AM, Dinh Nguyen gills702@gmail.com wrote:
This commit is an add-on to f6c4191f. There are a few registers where consecutive writes to the same location should be avoided or have a delay.
According to Synopsys, here is a list of the registers and bit(s) where consecutive writes should be avoided or a delay is required:
DMA Registers: Register 0 Bit 7 Register 6 All bits except for 24, 16-13, 2-1.
GMAC Registers: Registers 0-3 All bits Registers 6-7 All bits Register 10 All bits Register 11 All bits except for 5-6. Registers 16-47 All bits Register 48 All bits except for 18-16, 14. Register 448 Bit 4. Register 459 Bits 0-3.
Reviewd-by: Matthew Gerlach mgerlach@altera.com Signed-off-by: Dinh Nguyen dinguyen@altera.com
Applied to next, thanks.
-Joe