The cp_delay() function was introduced because of a missing 'volatile' attribute to the 'asm' statement in get_cr() which led to the 'mrc' instruction in get_cr() being optimised out eventually. This has been fixed in commit 53fd4b8c22bb ("arm: mmu: Add missing volatile for reading SCTLR register") but the bogus cp_delay() function which was introduced as a workaround for the malfunctioning get_cr() was never removed.
Signed-off-by: Lothar Waßmann LW@KARO-electronics.de --- arch/arm/lib/cache-cp15.c | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-)
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index e9bbcf5..2334edb 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -22,16 +22,6 @@ __weak void arm_init_domains(void) { }
-static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++) - nop(); - asm volatile("" : : : "memory"); -} - void set_section_dcache(int section, enum dcache_option option) { #ifdef CONFIG_ARMV7_LPAE @@ -196,7 +186,6 @@ static inline void mmu_setup(void)
/* and enable the mmu */ reg = get_cr(); /* get control reg. */ - cp_delay(); set_cr(reg | CR_M); }
@@ -214,7 +203,6 @@ static void cache_enable(uint32_t cache_bit) if ((cache_bit == CR_C) && !mmu_enabled()) mmu_setup(); reg = get_cr(); /* get control reg. */ - cp_delay(); set_cr(reg | cache_bit); }
@@ -224,7 +212,6 @@ static void cache_disable(uint32_t cache_bit) uint32_t reg;
reg = get_cr(); - cp_delay();
if (cache_bit == CR_C) { /* if cache isn;t enabled no need to disable */ @@ -234,7 +221,7 @@ static void cache_disable(uint32_t cache_bit) cache_bit |= CR_M; } reg = get_cr(); - cp_delay(); + if (cache_bit == (CR_C | CR_M)) flush_dcache_all(); set_cr(reg & ~cache_bit);