This series adds support for enhanced SPI modes. It was tested on a K210 (DWC SSI with QSPI flash).
If anyone has a designware device with QSPI flash attached (especially a DW SSI APB device), I'd greatly appreciate them testing out this patch series.
Many of the earlier patches in this series are general fixups and can be split off/merged separately if desired.
Changes in v2: - Add more information to exec_op debug message - Actually mask interrupts - Merge CAP_{DUAL,QUAD,OCTAL} into CAP_ENHANCED - Fix some inconsistencies in register naming and usage - Moved some hunks between commits so things make more sense
Sean Anderson (14): cmd: sf: Display errno on erase failure cmd: sf: Print error on test failure mtd: spi-nor-core: Fix typo in documentation mtd: spi-mem: Export spi_mem_default_supports_op spi: spi-mem: Add debug message for spi-mem ops spi: dw: Log status register on timeout spi: dw: Actually mask interrupts spi: dw: Switch to capabilities spi: dw: Rewrite poll_transfer logic spi: dw: Add ENHANCED cap spi: dw: Define registers for enhanced mode spi: dw: Support enhanced SPI spi: dw: Support clock stretching riscv: k210: Enable QSPI for spi3
arch/riscv/dts/k210-maix-bit.dts | 2 + cmd/sf.c | 29 +- drivers/spi/designware_spi.c | 647 +++++++++++++++++++++---------- drivers/spi/spi-mem.c | 7 + include/linux/mtd/spi-nor.h | 2 +- include/spi-mem.h | 3 + 6 files changed, 472 insertions(+), 218 deletions(-)