Re: [PATCH 1/3] arm64: dts: rk3399: sync rk3399.dtsi from 6.1-rc1

On 2022/10/25 15:52, Peter Robinson wrote:

Sync rk3399.dtsi and associated bindings includes. Fix up building of clk/rockchip/clk_rk3399.c for the changes as well as adjusting the rk3399-u-boot.dtsi for the new upstream pieces.

Signed-off-by: Peter Robinson pbrobinson@gmail.com

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

arch/arm/dts/rk3399-opp.dtsi | 6 +- arch/arm/dts/rk3399-u-boot.dtsi | 36 ++-- arch/arm/dts/rk3399.dtsi | 200 ++++++++++++++++++++--- drivers/clk/rockchip/clk_rk3399.c | 2 +- include/dt-bindings/clock/rk3399-cru.h | 24 +-- include/dt-bindings/power/rk3399-power.h | 1 + 6 files changed, 206 insertions(+), 63 deletions(-)

diff --git a/arch/arm/dts/rk3399-opp.dtsi b/arch/arm/dts/rk3399-opp.dtsi index da41cd81ebb..fee5e711127 100644 --- a/arch/arm/dts/rk3399-opp.dtsi +++ b/arch/arm/dts/rk3399-opp.dtsi @@ -4,7 +4,7 @@ */

/ {

• cluster0_opp: opp-table0 {

• cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared;

@@ -35,7 +35,7 @@ }; };

• cluster1_opp: opp-table1 {

• cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared;

@@ -74,7 +74,7 @@ }; };

• gpu_opp_table: opp-table2 {

• gpu_opp_table: opp-table-2 { compatible = "operating-points-v2";

  opp00 {

diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 3c1a15fe51b..2fa8f25a3e1 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -20,38 +20,12 @@ reg = <0x0 0xff620000 0x0 0x100>; };

• dfi: dfi@ff630000 {

• u-boot,dm-pre-reloc;
  

• reg = <0x00 0xff630000 0x00 0x4000>;
  

• compatible = "rockchip,rk3399-dfi";
  

• rockchip,pmu = <&pmugrf>;
  

• clocks = <&cru PCLK_DDR_MON>;
  

• clock-names = "pclk_ddr_mon";
  

• };

• rng: rng@ff8b8000 { compatible = "rockchip,cryptov1-rng"; reg = <0x0 0xff8b8000 0x0 0x1000>; status = "okay"; };

• dmc: dmc {

• u-boot,dm-pre-reloc;
  

• compatible = "rockchip,rk3399-dmc";
  

• devfreq-events = <&dfi>;
  

• interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
  

• clocks = <&cru SCLK_DDRCLK>;
  

• clock-names = "dmc_clk";
  

• reg = <0x0 0xffa80000 0x0 0x0800
  

•        0x0 0xffa80800 0x0 0x1800
  

•        0x0 0xffa82000 0x0 0x2000
  

•        0x0 0xffa84000 0x0 0x1000
  

•        0x0 0xffa88000 0x0 0x0800
  

•        0x0 0xffa88800 0x0 0x1800
  

•        0x0 0xffa8a000 0x0 0x2000
  

•        0x0 0xffa8c000 0x0 0x1000>;
  

• };

• pmusgrf: syscon@ff330000 { u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-pmusgrf", "syscon";

@@ -88,6 +62,16 @@ u-boot,dm-pre-reloc; };

+&dfi {

• u-boot,dm-pre-reloc;
• status = "okay";

+};

+&dmc {

• u-boot,dm-pre-reloc;
• status = "okay";

+};

• &emmc_phy { u-boot,dm-pre-reloc; };

diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index 3871c7fd83b..92c2207e686 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -124,6 +124,12 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;

• 	thermal-idle {
  

• 		#cooling-cells = <2>;
  

• 		duration-us = <10000>;
  

• 		exit-latency-us = <500>;
  

• 	};
  

  };

  cpu_b1: cpu@101 {

@@ -136,6 +142,12 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;

• 	thermal-idle {
  

• 		#cooling-cells = <2>;
  

• 		duration-us = <10000>;
  

• 		exit-latency-us = <500>;
  

• 	};
  

  };

  idle-states {

@@ -166,6 +178,15 @@ ports = <&vopl_out>, <&vopb_out>; };

• dmc: memory-controller {

• compatible = "rockchip,rk3399-dmc";
  

• rockchip,pmu = <&pmugrf>;
  

• devfreq-events = <&dfi>;
  

• clocks = <&cru SCLK_DDRC>;
  

• clock-names = "dmc_clk";
  

• status = "disabled";
  

• };
• pmu_a53 { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;

@@ -361,6 +382,54 @@ status = "disabled"; };

• debug@fe430000 {

• compatible = "arm,coresight-cpu-debug", "arm,primecell";
  

• reg = <0 0xfe430000 0 0x1000>;
  

• clocks = <&cru PCLK_COREDBG_L>;
  

• clock-names = "apb_pclk";
  

• cpu = <&cpu_l0>;
  

• };
• debug@fe432000 {

• compatible = "arm,coresight-cpu-debug", "arm,primecell";
  

• reg = <0 0xfe432000 0 0x1000>;
  

• clocks = <&cru PCLK_COREDBG_L>;
  

• clock-names = "apb_pclk";
  

• cpu = <&cpu_l1>;
  

• };
• debug@fe434000 {

• compatible = "arm,coresight-cpu-debug", "arm,primecell";
  

• reg = <0 0xfe434000 0 0x1000>;
  

• clocks = <&cru PCLK_COREDBG_L>;
  

• clock-names = "apb_pclk";
  

• cpu = <&cpu_l2>;
  

• };
• debug@fe436000 {

• compatible = "arm,coresight-cpu-debug", "arm,primecell";
  

• reg = <0 0xfe436000 0 0x1000>;
  

• clocks = <&cru PCLK_COREDBG_L>;
  

• clock-names = "apb_pclk";
  

• cpu = <&cpu_l3>;
  

• };
• debug@fe610000 {

• compatible = "arm,coresight-cpu-debug", "arm,primecell";
  

• reg = <0 0xfe610000 0 0x1000>;
  

• clocks = <&cru PCLK_COREDBG_B>;
  

• clock-names = "apb_pclk";
  

• cpu = <&cpu_b0>;
  

• };
• debug@fe710000 {

• compatible = "arm,coresight-cpu-debug", "arm,primecell";
  

• reg = <0 0xfe710000 0 0x1000>;
  

• clocks = <&cru PCLK_COREDBG_B>;
  

• clock-names = "apb_pclk";
  

• cpu = <&cpu_b1>;
  

• };
• usbdrd3_0: usb@fe800000 { compatible = "rockchip,rk3399-dwc3"; #address-cells = <2>;

@@ -1235,6 +1304,16 @@ status = "disabled"; };

• dfi: dfi@ff630000 {

• reg = <0x00 0xff630000 0x00 0x4000>;
  

• compatible = "rockchip,rk3399-dfi";
  

• rockchip,pmu = <&pmugrf>;
  

• interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
  

• clocks = <&cru PCLK_DDR_MON>;
  

• clock-names = "pclk_ddr_mon";
  

• status = "disabled";
  

• };
• vpu: video-codec@ff650000 { compatible = "rockchip,rk3399-vpu"; reg = <0x0 0xff650000 0x0 0x800>;

@@ -1251,7 +1330,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff650800 0x0 0x40>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;

• interrupt-names = "vpu_mmu";
  

  clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; clock-names = "aclk", "iface"; #iommu-cells = <0>;

@@ -1273,7 +1351,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;

• interrupt-names = "vdec_mmu";
  

  clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; clock-names = "aclk", "iface"; power-domains = <&power RK3399_PD_VDU>;

@@ -1284,7 +1361,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff670800 0x0 0x40>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;

• interrupt-names = "iep_mmu";
  

  clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; clock-names = "aclk", "iface"; #iommu-cells = <0>;

@@ -1356,9 +1432,11 @@ clock-names = "apb_pclk"; };

• pmucru: pmu-clock-controller@ff750000 {

• pmucru: clock-controller@ff750000 { compatible = "rockchip,rk3399-pmucru"; reg = <0x0 0xff750000 0x0 0x1000>;

• clocks = <&xin24m>;
  

• clock-names = "xin24m";
  

  rockchip,grf = <&pmugrf>; #clock-cells = <1>; #reset-cells = <1>;

@@ -1369,6 +1447,8 @@ cru: clock-controller@ff760000 { compatible = "rockchip,rk3399-cru"; reg = <0x0 0xff760000 0x0 0x1000>;

• clocks = <&xin24m>;
  

• clock-names = "xin24m";
  

  rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>;

@@ -1382,7 +1462,8 @@ <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, <&cru ACLK_VIO>, <&cru ACLK_HDCP>, <&cru ACLK_GIC_PRE>,

• 	<&cru PCLK_DDR>;
  

• 	<&cru PCLK_DDR>,
  

• 	<&cru ACLK_VDU>;
  

  assigned-clock-rates = <594000000>, <800000000>, <1000000000>,

@@ -1393,7 +1474,8 @@ <100000000>, <50000000>, <400000000>, <400000000>, <200000000>,

• 	 <200000000>;
  

• 	 <200000000>,
  

• 	 <400000000>;
  

  };

  grf: syscon@ff770000 {

@@ -1477,6 +1559,7 @@ reg = <0xf780 0x24>; clocks = <&sdhci>; clock-names = "emmcclk";

• 	drive-impedance-ohm = <50>;
  #phy-cells = <0>;
  status = "disabled";
  

  };

@@ -1487,7 +1570,6 @@ clock-names = "refclk"; #phy-cells = <1>; resets = <&cru SRST_PCIEPHY>;

• 	drive-impedance-ohm = <50>;
  reset-names = "phy";
  status = "disabled";
  

  };

@@ -1582,8 +1664,9 @@ dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;

• pinctrl-names = "default";
  

• pinctrl-names = "bclk_on", "bclk_off";
  

  pinctrl-0 = <&i2s0_8ch_bus>;

• pinctrl-1 = <&i2s0_8ch_bus_bclk_off>;
  

  power-domains = <&power RK3399_PD_SDIOAUDIO>; #sound-dai-cells = <0>; status = "disabled";

@@ -1619,7 +1702,7 @@

vopl: vop@ff8f0000 { compatible = "rockchip,rk3399-vop-lit";

• reg = <0x0 0xff8f0000 0x0 0x3efc>;
  

• reg = <0x0 0xff8f0000 0x0 0x2000>, <0x0 0xff8f2000 0x0 0x400>;
  

  interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; assigned-clock-rates = <400000000>, <100000000>;

@@ -1666,7 +1749,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff8f3f00 0x0 0x100>; interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;

• interrupt-names = "vopl_mmu";
  

  clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; clock-names = "aclk", "iface"; power-domains = <&power RK3399_PD_VOPL>;

@@ -1676,7 +1758,7 @@

vopb: vop@ff900000 { compatible = "rockchip,rk3399-vop-big";

• reg = <0x0 0xff900000 0x0 0x3efc>;
  

• reg = <0x0 0xff900000 0x0 0x2000>, <0x0 0xff902000 0x0 0x1000>;
  

  interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; assigned-clock-rates = <400000000>, <100000000>;

@@ -1723,7 +1805,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff903f00 0x0 0x100>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;

• interrupt-names = "vopb_mmu";
  

  clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; clock-names = "aclk", "iface"; power-domains = <&power RK3399_PD_VOPB>;

@@ -1761,7 +1842,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;

• interrupt-names = "isp0_mmu";
  

  clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; clock-names = "aclk", "iface"; #iommu-cells = <0>;

@@ -1769,11 +1849,36 @@ rockchip,disable-mmu-reset; };

• isp1: isp1@ff920000 {

• compatible = "rockchip,rk3399-cif-isp";
  

• reg = <0x0 0xff920000 0x0 0x4000>;
  

• interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
  

• clocks = <&cru SCLK_ISP1>,
  

• 	 <&cru ACLK_ISP1_WRAPPER>,
  

• 	 <&cru HCLK_ISP1_WRAPPER>;
  

• clock-names = "isp", "aclk", "hclk";
  

• iommus = <&isp1_mmu>;
  

• phys = <&mipi_dsi1>;
  

• phy-names = "dphy";
  

• power-domains = <&power RK3399_PD_ISP1>;
  

• status = "disabled";
  

• ports {
  

• 	#address-cells = <1>;
  

• 	#size-cells = <0>;
  

• 	port@0 {
  

• 		reg = <0>;
  

• 		#address-cells = <1>;
  

• 		#size-cells = <0>;
  

• 	};
  

• };
  

• };
• isp1_mmu: iommu@ff924000 { compatible = "rockchip,iommu"; reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;

• interrupt-names = "isp1_mmu";
  

  clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; clock-names = "aclk", "iface"; #iommu-cells = <0>;

@@ -1802,10 +1907,10 @@ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>,

• 	 <&cru PLL_VPLL>,
  

• 	 <&cru SCLK_HDMI_CEC>,
   <&cru PCLK_VIO_GRF>,
  

• 	 <&cru SCLK_HDMI_CEC>;
  

• clock-names = "iahb", "isfr", "vpll", "grf", "cec";
  

• 	 <&cru PLL_VPLL>;
  

• clock-names = "iahb", "isfr", "cec", "grf", "ref";
  

  power-domains = <&power RK3399_PD_HDCP>; reg-io-width = <4>; rockchip,grf = <&grf>;

@@ -1878,6 +1983,7 @@ rockchip,grf = <&grf>; #address-cells = <1>; #size-cells = <0>;

• #phy-cells = <0>;
  

  status = "disabled";

  ports {

@@ -1958,7 +2064,7 @@ #size-cells = <2>; ranges;

• gpio0: gpio0@ff720000 {
  

• gpio0: gpio@ff720000 {
  compatible = "rockchip,gpio-bank";
  reg = <0x0 0xff720000 0x0 0x100>;
  clocks = <&pmucru PCLK_GPIO0_PMU>;
  

@@ -1971,7 +2077,7 @@ #interrupt-cells = <0x2>; };

• gpio1: gpio1@ff730000 {
  

• gpio1: gpio@ff730000 {
  compatible = "rockchip,gpio-bank";
  reg = <0x0 0xff730000 0x0 0x100>;
  clocks = <&pmucru PCLK_GPIO1_PMU>;
  

@@ -1984,7 +2090,7 @@ #interrupt-cells = <0x2>; };

• gpio2: gpio2@ff780000 {
  

• gpio2: gpio@ff780000 {
  compatible = "rockchip,gpio-bank";
  reg = <0x0 0xff780000 0x0 0x100>;
  clocks = <&cru PCLK_GPIO2>;
  

@@ -1997,7 +2103,7 @@ #interrupt-cells = <0x2>; };

• gpio3: gpio3@ff788000 {
  

• gpio3: gpio@ff788000 {
  compatible = "rockchip,gpio-bank";
  reg = <0x0 0xff788000 0x0 0x100>;
  clocks = <&cru PCLK_GPIO3>;
  

@@ -2010,7 +2116,7 @@ #interrupt-cells = <0x2>; };

• gpio4: gpio4@ff790000 {
  

• gpio4: gpio@ff790000 {
  compatible = "rockchip,gpio-bank";
  reg = <0x0 0xff790000 0x0 0x100>;
  clocks = <&cru PCLK_GPIO4>;
  

@@ -2108,12 +2214,40 @@ output-low; };

• pcfg_input_enable: pcfg-input-enable {
  

• 	input-enable;
  

• };
  

• pcfg_input_pull_up: pcfg-input-pull-up {
  

• 	input-enable;
  

• 	bias-pull-up;
  

• 	drive-strength = <2>;
  

• };
  

• pcfg_input_pull_down: pcfg-input-pull-down {
  

• 	input-enable;
  

• 	bias-pull-down;
  

• 	drive-strength = <2>;
  

• };
  

• clock { clk_32k: clk-32k { rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; }; };

• cif {
  

• 	cif_clkin: cif-clkin {
  

• 		rockchip,pins =
  

• 			<2 RK_PB2 3 &pcfg_pull_none>;
  

• 	};
  

• 	cif_clkouta: cif-clkouta {
  

• 		rockchip,pins =
  

• 			<2 RK_PB3 3 &pcfg_pull_none>;
  

• 	};
  

• };
  

• edp { edp_hpd: edp-hpd { rockchip,pins =

@@ -2276,6 +2410,19 @@ <3 RK_PD7 1 &pcfg_pull_none>, <4 RK_PA0 1 &pcfg_pull_none>; };

• 	i2s0_8ch_bus_bclk_off: i2s0-8ch-bus-bclk-off {
  

• 		rockchip,pins =
  

• 			<3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,
  

• 			<3 RK_PD1 1 &pcfg_pull_none>,
  

• 			<3 RK_PD2 1 &pcfg_pull_none>,
  

• 			<3 RK_PD3 1 &pcfg_pull_none>,
  

• 			<3 RK_PD4 1 &pcfg_pull_none>,
  

• 			<3 RK_PD5 1 &pcfg_pull_none>,
  

• 			<3 RK_PD6 1 &pcfg_pull_none>,
  

• 			<3 RK_PD7 1 &pcfg_pull_none>,
  

• 			<4 RK_PA0 1 &pcfg_pull_none>;
  

• 	};
  

  };

  i2s1 {

@@ -2287,6 +2434,15 @@ <4 RK_PA6 1 &pcfg_pull_none>, <4 RK_PA7 1 &pcfg_pull_none>; };

• 	i2s1_2ch_bus_bclk_off: i2s1-2ch-bus-bclk-off {
  

• 		rockchip,pins =
  

• 			<4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>,
  

• 			<4 RK_PA4 1 &pcfg_pull_none>,
  

• 			<4 RK_PA5 1 &pcfg_pull_none>,
  

• 			<4 RK_PA6 1 &pcfg_pull_none>,
  

• 			<4 RK_PA7 1 &pcfg_pull_none>;
  

• 	};
  

  };

  sdio0 {

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 97bf1c6e15b..e968ddf894b 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1049,7 +1049,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) * return 0 to satisfy clk_set_defaults during device probe. */ return 0;

• case SCLK_DDRCLK:

• case SCLK_TESTCLKOUT2: ret = rk3399_ddr_set_clk(priv->cru, rate); break; case PCLK_EFUSE1024NS:

diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 211faf8fa89..44e0a319f07 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -1,6 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /*

• Copyright (c) 2016 Rockchip Electronics Co. Ltd.

• • Author: Xing Zheng zhengxing@rock-chips.com

  */

  #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H

@@ -121,16 +122,17 @@ #define SCLK_DPHY_RX0_CFG 165 #define SCLK_RMII_SRC 166 #define SCLK_PCIEPHY_REF100M 167 -#define SCLK_USBPHY0_480M_SRC 168 -#define SCLK_USBPHY1_480M_SRC 169 -#define SCLK_DDRCLK 170 -#define SCLK_TESTOUT2 171 +#define SCLK_DDRC 168 +#define SCLK_TESTCLKOUT1 169 +#define SCLK_TESTCLKOUT2 170

#define DCLK_VOP0 180 #define DCLK_VOP1 181 #define DCLK_VOP0_DIV 182 #define DCLK_VOP1_DIV 183 #define DCLK_M0_PERILP 184 +#define DCLK_VOP0_FRAC 185 +#define DCLK_VOP1_FRAC 186

#define FCLK_CM0S 190

@@ -592,13 +594,13 @@ #define SRST_P_SPI0 214 #define SRST_P_SPI1 215 #define SRST_P_SPI2 216 -#define SRST_P_SPI4 217 -#define SRST_P_SPI5 218 +#define SRST_P_SPI3 217 +#define SRST_P_SPI4 218 #define SRST_SPI0 219 #define SRST_SPI1 220 #define SRST_SPI2 221 -#define SRST_SPI4 222 -#define SRST_SPI5 223 +#define SRST_SPI3 222 +#define SRST_SPI4 223

/* cru_softrst_con14 */ #define SRST_I2S0_8CH 224 @@ -720,8 +722,8 @@ #define SRST_H_CM0S_NOC 3 #define SRST_DBG_CM0S 4 #define SRST_PO_CM0S 5 -#define SRST_P_SPI3 6 -#define SRST_SPI3 7 +#define SRST_P_SPI6 6 +#define SRST_SPI6 7 #define SRST_P_TIMER_0_1 8 #define SRST_P_TIMER_0 9 #define SRST_P_TIMER_1 10 diff --git a/include/dt-bindings/power/rk3399-power.h b/include/dt-bindings/power/rk3399-power.h index 168b3bfbd6f..aedd8b180fe 100644 --- a/include/dt-bindings/power/rk3399-power.h +++ b/include/dt-bindings/power/rk3399-power.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __DT_BINDINGS_POWER_RK3399_POWER_H__ #define __DT_BINDINGS_POWER_RK3399_POWER_H__