Hi Francesco,
On Wed, Apr 6, 2022 at 8:53 AM Francesco Dolcini francesco.dolcini@toradex.com wrote:
Wait 1ms before issuing the first MRS command to write DDR3 Mode registers.
There is a requirement to wait a minimum time before issuing command to the DDR3 device, according to the JEDEC standard this time is 500us (after RESET_n is de-asserted until CKE becomes active) + tXPR (Reset CKE Exit time, maximum value 360ns).
It seems that for some reason this is not enforced by the MMDC controller.
Without this change we experienced random memory initialization failures with about 2% boot failure rate on specific problematic boards, after this change we were able to do more than 10.000 power-cycle without a single failure.
Glad you fixed this problem. Not an easy one!
Reviewed-by: Fabio Estevam festevam@denx.de