On 27 July 2016 at 14:28, Siva Durga Prasad Paladugu siva.durga.paladugu@xilinx.com wrote:
Hi Jagan,
-----Original Message----- From: Jagan Teki [mailto:jagannadh.teki@gmail.com] Sent: Wednesday, July 27, 2016 1:47 PM To: Siva Durga Prasad Paladugu sivadur@xilinx.com Cc: u-boot@lists.denx.de; Michal Simek michals@xilinx.com; Siva Durga Prasad Paladugu sivadur@xilinx.com Subject: Re: [PATCH v2 0/9] qspi: Add Quad and Dual mode support for Zynq QSPI
On 19 July 2016 at 21:18, Siva Durga Prasad Paladugu siva.durga.paladugu@xilinx.com wrote:
This series enables the Quad and dual modes support for zynq. It also contains fixes for issues found during testing of dual parallel and stacked modes.
Siva Durga Prasad Paladugu (9): spi: zynq_qspi: Add quad support for zynq qspi spi: zynq_qspi: Add support of Dual parallel and Dual stacked modes sf: Kconfig: Add SF_DUAL_FLASH config entry dts: zynq_zc706: update qspi node with is-dual and num-cs defconfig: zc706: Add dual modes support for zc706 spi: spi_flash: Correct flash size calculation spi: spi_flash: Correct bank select incase of dual stacked spi: spi_flash: Fix Bank selection calculation for Dual parallel spi: spi_flash: Set Quad enable bit of upper flash
All these patches were talking to spi about flash attributes which wrong, I thought you might have know all these. spi-nor framework is dealing all these pitfalls, if possible please do work on that.
I didn’t find any spi-nor framework in mainline when I sent these patches that’s why these are like this. How could I send without aware of spi-nor framework.
I'm just pointing an alternate approach, and either way please tune your approach better the one you added look not good to me.