This block provides clock and reset control for MIO (Media I/O) hardware blocks such as USB2.0, SD card, eMMC, etc.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/arm/dts/uniphier-common32.dtsi | 6 ++++++ arch/arm/dts/uniphier-ph1-ld4.dtsi | 6 ++++++ arch/arm/dts/uniphier-ph1-pro4.dtsi | 6 ++++++ arch/arm/dts/uniphier-ph1-pro5.dtsi | 6 ++++++ arch/arm/dts/uniphier-ph1-sld3.dtsi | 8 ++++++++ arch/arm/dts/uniphier-ph1-sld8.dtsi | 6 ++++++ arch/arm/dts/uniphier-proxstream2.dtsi | 6 ++++++ 7 files changed, 44 insertions(+)
diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi index 43e5bea..59511bd 100644 --- a/arch/arm/dts/uniphier-common32.dtsi +++ b/arch/arm/dts/uniphier-common32.dtsi @@ -74,6 +74,12 @@ reg = <0x58c00000 0x400>, <0x59800000 0x2000>; };
+ mio: mioctrl@59810000 { + /* specify compatible in each SoC DTSI */ + reg = <0x59810000 0x800>; + #clock-cells = <1>; + }; + peri: perictrl@59820000 { /* specify compatible in each SoC DTSI */ reg = <0x59820000 0x200>; diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi index 5843097..628a397 100644 --- a/arch/arm/dts/uniphier-ph1-ld4.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi @@ -157,6 +157,12 @@ clock-frequency = <36864000>; };
+&mio { + compatible = "socionext,ph1-ld4-mioctrl"; + clock-names = "stdmac", "ehci"; + clocks = <&sysctrl 10>, <&sysctrl 18>; +}; + &peri { compatible = "socionext,ph1-ld4-perictrl"; clock-names = "uart", "i2c"; diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi index 0c2f02f..bfffe94 100644 --- a/arch/arm/dts/uniphier-ph1-pro4.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi @@ -197,6 +197,12 @@ clock-frequency = <73728000>; };
+&mio { + compatible = "socionext,ph1-pro4-mioctrl"; + clock-names = "stdmac", "ehci"; + clocks = <&sysctrl 10>, <&sysctrl 18>; +}; + &peri { compatible = "socionext,ph1-pro4-perictrl"; clock-names = "uart", "fi2c"; diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi index 305114c..087b25a 100644 --- a/arch/arm/dts/uniphier-ph1-pro5.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi @@ -191,6 +191,12 @@ clock-frequency = <73728000>; };
+&mio { + compatible = "socionext,ph1-pro5-mioctrl"; + clock-names = "stdmac"; + clocks = <&sysctrl 10>; +}; + &peri { compatible = "socionext,ph1-pro5-perictrl"; clock-names = "uart", "fi2c"; diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi index c7a8902..91c9ba5 100644 --- a/arch/arm/dts/uniphier-ph1-sld3.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi @@ -178,6 +178,14 @@ reg = <0x59800000 0x2000>; };
+ mio: mioctrl@59810000 { + compatible = "socionext,ph1-sld3-mioctrl"; + reg = <0x59810000 0x800>; + #clock-cells = <1>; + clock-names = "stdmac", "ehci"; + clocks = <&sysctrl 10>, <&sysctrl 18>; + }; + usb0: usb@5a800100 { compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi index 7a26b4a..b9ef401 100644 --- a/arch/arm/dts/uniphier-ph1-sld8.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi @@ -157,6 +157,12 @@ clock-frequency = <80000000>; };
+&mio { + compatible = "socionext,ph1-sld8-mioctrl"; + clock-names = "stdmac", "ehci"; + clocks = <&sysctrl 10>, <&sysctrl 18>; +}; + &peri { compatible = "socionext,ph1-sld8-perictrl"; clock-names = "uart", "i2c"; diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi index f2faf25..a70b135 100644 --- a/arch/arm/dts/uniphier-proxstream2.dtsi +++ b/arch/arm/dts/uniphier-proxstream2.dtsi @@ -202,6 +202,12 @@ clock-frequency = <88900000>; };
+&mio { + compatible = "socionext,ph1-pro5-mioctrl"; + clock-names = "stdmac"; + clocks = <&sysctrl 10>; +}; + &peri { compatible = "socionext,proxstream2-perictrl"; clock-names = "uart", "fi2c";