RE: [PATCH 56/57] ppc: Remove T4160RDB board

22 Feb 2021

Hi Tom,
...
-----Original Message-----
From: U-Boot u-boot-bounces@lists.denx.de On Behalf Of Tom Rini
Sent: Sunday, February 21, 2021 9:07 AM
To: u-boot@lists.denx.de
Cc: Priyanka Jain priyanka.jain@nxp.com
Subject: [PATCH 56/57] ppc: Remove T4160RDB board
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.  As this is the last ARCH_T1023 platform, remove that support
as well.
Cc: Priyanka Jain priyanka.jain@nxp.com
Signed-off-by: Tom Rini trini@konsulko.com

arch/powerpc/cpu/mpc85xx/Kconfig              |  39 +-
 arch/powerpc/cpu/mpc85xx/Makefile             |   2 -
 arch/powerpc/cpu/mpc85xx/fdt.c                |   5 +-
 .../powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c |   2 +-
 arch/powerpc/cpu/mpc85xx/speed.c              |   3 +-
 arch/powerpc/cpu/mpc85xx/t4240_serdes.c       | 202 ------
 arch/powerpc/include/asm/config_mpc85xx.h     |   5 +-
 arch/powerpc/include/asm/fsl_secure_boot.h    |   1 -
 arch/powerpc/include/asm/immap_85xx.h         |   4 +-
 board/freescale/t4rdb/Kconfig                 |  14 -
 board/freescale/t4rdb/MAINTAINERS             |   8 -
 board/freescale/t4rdb/Makefile                |  19 -
 board/freescale/t4rdb/cpld.c                  | 129 ----
 board/freescale/t4rdb/cpld.h                  |  48 --
 board/freescale/t4rdb/ddr.c                   | 128 ----
 board/freescale/t4rdb/ddr.h                   |  77 --
 board/freescale/t4rdb/eth.c                   | 152 ----
 board/freescale/t4rdb/law.c                   |  30 -
 board/freescale/t4rdb/pci.c                   |  25 -
 board/freescale/t4rdb/spl.c                   |  98 ---
 board/freescale/t4rdb/t4240rdb.c              | 153 ----
 board/freescale/t4rdb/t4_pbi.cfg              |  27 -
 board/freescale/t4rdb/t4_sd_rcw.cfg           |   7 -
 board/freescale/t4rdb/t4rdb.h                 |  17 -
 board/freescale/t4rdb/tlb.c                   | 123 ----
 configs/T4160RDB_defconfig                    |  57 --
 configs/T4240RDB_SDCARD_defconfig             |  78 --
 configs/T4240RDB_defconfig                    |  66 --
DM_MMC had already been in use for T4240RDB. The board is still in maintaining.
Can we keep it?
Thanks.
...
drivers/ddr/fsl/Kconfig                       |   3 +-
 drivers/net/Kconfig                           |   1 -
 drivers/net/fm/Makefile                       |   1 -
 include/configs/T4240RDB.h                    | 667 ------------------
 32 files changed, 9 insertions(+), 2182 deletions(-)
 delete mode 100644 board/freescale/t4rdb/Kconfig
 delete mode 100644 board/freescale/t4rdb/MAINTAINERS
 delete mode 100644 board/freescale/t4rdb/Makefile
 delete mode 100644 board/freescale/t4rdb/cpld.c
 delete mode 100644 board/freescale/t4rdb/cpld.h
 delete mode 100644 board/freescale/t4rdb/ddr.c
 delete mode 100644 board/freescale/t4rdb/ddr.h
 delete mode 100644 board/freescale/t4rdb/eth.c
 delete mode 100644 board/freescale/t4rdb/law.c
 delete mode 100644 board/freescale/t4rdb/pci.c
 delete mode 100644 board/freescale/t4rdb/spl.c
 delete mode 100644 board/freescale/t4rdb/t4240rdb.c
 delete mode 100644 board/freescale/t4rdb/t4_pbi.cfg
 delete mode 100644 board/freescale/t4rdb/t4_sd_rcw.cfg
 delete mode 100644 board/freescale/t4rdb/t4rdb.h
 delete mode 100644 board/freescale/t4rdb/tlb.c
 delete mode 100644 configs/T4160RDB_defconfig
 delete mode 100644 configs/T4240RDB_SDCARD_defconfig
 delete mode 100644 configs/T4240RDB_defconfig
 delete mode 100644 include/configs/T4240RDB.h

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig
b/arch/powerpc/cpu/mpc85xx/Kconfig
index 42c4d1f0399e..143ddaec2e6a 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -179,13 +179,6 @@ config TARGET_T2080RDB
   imply CMD_SATA
   imply PANIC_HANG
-config TARGET_T4160RDB

bool "Support T4160RDB"
select ARCH_T4160
select SUPPORT_SPL
select PHYS_64BIT
imply PANIC_HANG


config TARGET_T4240RDB
   bool "Support T4240RDB"
   select ARCH_T4240
@@ -810,31 +803,6 @@ config ARCH_T2080
   imply CMD_REGINFO
   imply FSL_SATA
-config ARCH_T4160

bool
select E500MC
select E6500
select FSL_LAW
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A004468
select SYS_FSL_ERRATUM_A005871
select SYS_FSL_ERRATUM_A006379
select SYS_FSL_ERRATUM_A006593
select SYS_FSL_ERRATUM_A007186
select SYS_FSL_ERRATUM_A007798
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
select FSL_IFC
imply CMD_SATA
imply CMD_NAND
imply CMD_REGINFO
imply FSL_SATA


config ARCH_T4240
   bool
   select E500MC
@@ -903,8 +871,7 @@ config NXP_ESBC
 config MAX_CPUS
   int "Maximum number of CPUs permitted for MPC85xx"
   default 12 if ARCH_T4240

default 8 if ARCH_P4080 || \
     ARCH_T4160




default 8 if ARCH_P4080
default 4 if ARCH_B4860 || \
    ARCH_P2041 || \
    ARCH_P3041 || \

@@ -962,7 +929,6 @@ config SYS_CCSRBAR_DEFAULT
   			ARCH_T1040	|| \
   			ARCH_T1042	|| \
   			ARCH_T2080	|| \

		ARCH_T4160	|| \
	ARCH_T4240

default 0xe0000000 if ARCH_QEMU_E500
help

@@ -1147,7 +1113,6 @@ config SYS_FSL_NUM_LAWS
   		ARCH_P4080	|| \
   		ARCH_P5040	|| \
   		ARCH_T2080	|| \

	ARCH_T4160	|| \
ARCH_T4240

default 16 if	ARCH_T1024	|| \
	ARCH_T1040	|| \

@@ -1232,7 +1197,6 @@ config SYS_FSL_IFC_CLK_DIV
   		ARCH_T1024	|| \
   		ARCH_T1040	|| \
   		ARCH_T1042	|| \

	ARCH_T4160	|| \
ARCH_T4240

default 1
help

@@ -1267,7 +1231,6 @@ source "board/freescale/p2041rdb/Kconfig"
 source "board/freescale/qemu-ppce500/Kconfig"
 source "board/freescale/t208xqds/Kconfig"
 source "board/freescale/t208xrdb/Kconfig"
-source "board/freescale/t4rdb/Kconfig"
 source "board/keymile/Kconfig"
 source "board/sbc8548/Kconfig"
 source "board/socrates/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile
b/arch/powerpc/cpu/mpc85xx/Makefile
index 4d9a07b5d9c3..ebd1bb667ea5 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -42,7 +42,6 @@ obj-$(CONFIG_ARCH_P3041) += p3041_ids.o
 obj-$(CONFIG_ARCH_P4080) += p4080_ids.o
 obj-$(CONFIG_ARCH_P5040) += p5040_ids.o
 obj-$(CONFIG_ARCH_T4240) += t4240_ids.o
-obj-$(CONFIG_ARCH_T4160) += t4240_ids.o
 obj-$(CONFIG_ARCH_B4420) += b4860_ids.o
 obj-$(CONFIG_ARCH_B4860) += b4860_ids.o
 obj-$(CONFIG_ARCH_T1040) += t1040_ids.o
@@ -76,7 +75,6 @@ obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o
 obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o
 obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o
 obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o
-obj-$(CONFIG_ARCH_T4160) += t4240_serdes.o
 obj-$(CONFIG_ARCH_B4420) += b4860_serdes.o
 obj-$(CONFIG_ARCH_B4860) += b4860_serdes.o
 obj-$(CONFIG_ARCH_BSC9132) += bsc9132_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c
b/arch/powerpc/cpu/mpc85xx/fdt.c
index 7d168e3c9a0e..3f2fc062b2b0 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -527,8 +527,7 @@ static void fdt_fixup_usb(void *fdt)
 #define fdt_fixup_usb(x)
 #endif
-#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \

defined(CONFIG_ARCH_T4160)

+#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240)
 void fdt_fixup_dma3(void *blob)
 {
   /* the 3rd DMA is not functional if SRIO2 is chosen */
@@ -545,7 +544,7 @@ void fdt_fixup_dma3(void *blob)
   case 0x29:
   case 0x2d:
   case 0x2e:
-#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
+#elif defined(CONFIG_ARCH_T4240)
   u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
   			    FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
   srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index ee5015ec8f3e..5bf0047930fe 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -392,7 +392,7 @@ const char *serdes_clock_to_string(u32 clock)
   case SRDS_PLLCR0_RFCK_SEL_161_13:
   	return "161.1328123";
   default:
-#if defined(CONFIG_TARGET_T4240QDS) ||
defined(CONFIG_TARGET_T4160QDS)
+#if defined(CONFIG_TARGET_T4240QDS)
   	return "???";
 #else
   	return "122.88";
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c
b/arch/powerpc/cpu/mpc85xx/speed.c
index 5a545a6d6412..89c56f9c606d 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -126,8 +126,7 @@ void get_sys_info(sys_info_t *sys_info)
    * it uses 6.
    * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
    */
-#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \

defined(CONFIG_ARCH_T2080)

+#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T2080)
   svr = get_svr();
   switch (SVR_SOC_VER(svr)) {
   case SVR_T4240:
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index a8c0c47f4af1..61402e84ef62 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -262,208 +262,6 @@ static const struct serdes_config serdes4_cfg_tbl[] =
{
   {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
   {}
 };
-#elif defined(CONFIG_ARCH_T4160)
-static const struct serdes_config serdes1_cfg_tbl[] = {

/* SerDes 1 */
{1, {NONE, NONE, NONE, NONE,
XAUI_FM1_MAC10, XAUI_FM1_MAC10,


XAUI_FM1_MAC10, XAUI_FM1_MAC10} },


{2, {NONE, NONE, NONE, NONE,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,


HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },


{4, {NONE, NONE, NONE, NONE,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,


HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },


{27, {NONE, NONE, NONE, NONE,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,


SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },


{28, {NONE, NONE, NONE, NONE,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,


SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },


{35, {NONE, NONE, NONE, NONE,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,


SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },


{36, {NONE, NONE, NONE, NONE,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,


SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },


{37, {NONE, NONE, NONE, NONE,
NONE, NONE, QSGMII_FM1_A, NONE} },


{38, {NONE, NONE, NONE, NONE,
NONE, NONE, QSGMII_FM1_A, NONE} },


{}

-};
-static const struct serdes_config serdes2_cfg_tbl[] = {

/* SerDes 2 */
{6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,


SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,


SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },


{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,


SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,


SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },


{12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,


SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,


SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },


{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,


SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,


SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },


{15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,


SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,


SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },


{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,


SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,


SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },


{21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,


SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,


SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },


{22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,


SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,


SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },


{24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,


SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,


SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },


{25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,


SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,


SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },


{26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,


SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,


NONE, NONE} },


{27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,


SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,


SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },


{28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,


SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,


SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },


{35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,


SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,


SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },


{36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,


SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,


SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },


{37, {NONE, NONE, QSGMII_FM2_B, NONE,
NONE, NONE, QSGMII_FM2_A, NONE} },


{38, {NONE, NONE, QSGMII_FM2_B, NONE,
NONE, NONE, QSGMII_FM2_A, NONE} },


{39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,


NONE, NONE, QSGMII_FM2_A, NONE} },


{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,


NONE, NONE, QSGMII_FM2_A, NONE} },


{45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,


NONE, NONE, QSGMII_FM2_A, NONE} },


{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,


NONE, NONE, QSGMII_FM2_A, NONE} },


{47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,


NONE, NONE, QSGMII_FM2_A, NONE} },


{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,


NONE, NONE, QSGMII_FM2_A, NONE} },


{49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,


NONE, NONE, QSGMII_FM2_A, NONE} },


{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,


NONE, NONE, QSGMII_FM2_A, NONE} },


{51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,


NONE, NONE, QSGMII_FM2_A, NONE} },


{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,


NONE, NONE, QSGMII_FM2_A, NONE} },


{53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,


NONE, NONE, QSGMII_FM2_A, NONE} },


{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,


NONE, NONE, QSGMII_FM2_A, NONE} },


{55, {NONE, XFI_FM1_MAC10,
XFI_FM2_MAC10, NONE,


SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,


SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },


{56, {NONE, XFI_FM1_MAC10,
XFI_FM2_MAC10, NONE,


SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,


SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },


{57, {NONE, XFI_FM1_MAC10,
XFI_FM2_MAC10, NONE,


SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,


NONE, NONE} },


{}

-};
-static const struct serdes_config serdes3_cfg_tbl[] = {

/* SerDes 3 */
{1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
{2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
{3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
{5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
{7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },


{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },


{11, {NONE, NONE, NONE, NONE,
PCIE2, PCIE2, PCIE2, PCIE2} },


{12, {NONE, NONE, NONE, NONE,
PCIE2, PCIE2, PCIE2, PCIE2} },


{13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
PCIE2, PCIE2, PCIE2, PCIE2} },


{14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
PCIE2, PCIE2, PCIE2, PCIE2} },


{15, {NONE, NONE, NONE, NONE,
SRIO1, SRIO1, SRIO1, SRIO1} },


{16, {NONE, NONE, NONE, NONE,
SRIO1, SRIO1, SRIO1, SRIO1} },


{17, {NONE, NONE, NONE, NONE,
SRIO1, SRIO1, SRIO1, SRIO1} },


{18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1} },


{19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1} },


{20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1} },


{}

-};
-static const struct serdes_config serdes4_cfg_tbl[] = {

/* SerDes 4 */
{3, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
{4, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
{5, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
{6, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
{7, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
{8, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
{9, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
{10, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
{11, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
{12, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
{13, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
{14, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
{15, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
{16, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
{18, {NONE, NONE, NONE, NONE, AURORA, AURORA, AURORA,

AURORA} },

{}

-}
-;
 #else
 #error "Need to define SerDes protocol"
 #endif
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index a52b31ec3950..6874692ae326 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -194,7 +194,7 @@
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_ESDHC_HC_BLK_ADDR
-#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
+#elif defined(CONFIG_ARCH_T4240)
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
@@ -209,9 +209,6 @@
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_SYS_NUM_FM2_DTSEC	8
 #define CONFIG_SYS_NUM_FM2_10GEC	1
-#if defined(CONFIG_ARCH_T4160)
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 1 }
-#endif
 #endif
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	5
 #define CONFIG_SYS_FSL_SRDS_1
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h
b/arch/powerpc/include/asm/fsl_secure_boot.h
index 991d75312a34..3a1d858ec645 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -21,7 +21,6 @@
#if defined(CONFIG_TARGET_B4860QDS) || \
   defined(CONFIG_TARGET_B4420QDS) || \

defined(CONFIG_TARGET_T4160QDS) || \
defined(CONFIG_TARGET_T4240QDS) || \
defined(CONFIG_TARGET_T2080QDS) || \
defined(CONFIG_TARGET_T2080RDB) || \

diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 1b3097772fb8..0c1c114c77b8 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1758,7 +1758,7 @@ typedef struct ccsr_gur {
 /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT	8
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK	0x3f
-#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
+#if defined(CONFIG_ARCH_T4240)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL		0xfc000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	26
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL		0x00fe0000
@@ -1870,7 +1870,7 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII
0x00100000
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE
0x00180000
 #endif
-#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
+#if defined(CONFIG_ARCH_T4240)
 #define FSL_CORENET_RCWSR13_EC1			0x60000000 /* bits 417..418
*/
 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII	0x00000000
 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO		0x40000000
diff --git a/board/freescale/t4rdb/Kconfig b/board/freescale/t4rdb/Kconfig
deleted file mode 100644
index a94a57e7feeb..000000000000
--- a/board/freescale/t4rdb/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_T4160RDB || TARGET_T4240RDB



-config SYS_BOARD

default "t4rdb"


-config SYS_VENDOR

default "freescale"


-config SYS_CONFIG_NAME

default "T4240RDB"


-source "board/freescale/common/Kconfig"



-endif
diff --git a/board/freescale/t4rdb/MAINTAINERS
b/board/freescale/t4rdb/MAINTAINERS
deleted file mode 100644
index 4ba5c3a546a3..000000000000
--- a/board/freescale/t4rdb/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-T4RDB BOARD
-#M:	Chunhe Lan Chunhe.Lan@freescale.com
-S:	Orphan (since 2018-05)
-F:	board/freescale/t4rdb/
-F:	include/configs/T4240RDB.h
-F:	configs/T4160RDB_defconfig
-F:	configs/T4240RDB_defconfig
-F:	configs/T4240RDB_SDCARD_defconfig
diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile
deleted file mode 100644
index 209983a24bd1..000000000000
--- a/board/freescale/t4rdb/Makefile
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# Copyright 2014 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#



-ifdef CONFIG_SPL_BUILD
-obj-y	+= spl.o
-else
-obj-$(CONFIG_TARGET_T4160RDB)	+= t4240rdb.o
-obj-$(CONFIG_TARGET_T4240RDB)	+= t4240rdb.o
-obj-y			+= cpld.o
-obj-y			+= eth.o
-obj-$(CONFIG_PCI)	+= pci.o
-endif



-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c
deleted file mode 100644
index d484509bc20a..000000000000
--- a/board/freescale/t4rdb/cpld.c
+++ /dev/null
@@ -1,129 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/**


Copyright 2014 Freescale Semiconductor







Author: Chunhe Lan Chunhe.Lan@freescale.com







This file provides support for the board-specific CPLD used on some



Freescale


reference boards.







The following macros need to be defined:







CONFIG_SYS_CPLD_BASE - The virtual address of the base of the



CPLD register map






*/


-#include <common.h>
-#include <command.h>
-#include <asm/io.h>



-#include "cpld.h"



-u8 cpld_read(unsigned int reg)
-{

void *p = (void *)CONFIG_SYS_CPLD_BASE;

return in_8(p + reg);

-}



-void cpld_write(unsigned int reg, u8 value)
-{

void *p = (void *)CONFIG_SYS_CPLD_BASE;

out_8(p + reg, value);

-}



-/**


Set the boot bank to the alternate bank


*/

-void cpld_set_altbank(void)
-{

u8 val, curbank, altbank, override;

val = CPLD_READ(vbank);
curbank = val & CPLD_BANK_SEL_MASK;

switch (curbank) {
case CPLD_SELECT_BANK0:
case CPLD_SELECT_BANK4:
altbank = CPLD_SELECT_BANK4;


CPLD_WRITE(vbank, altbank);


override = CPLD_READ(software_on);


CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN);


CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET);


break;


default:
printf("CPLD Altbank Fail: Invalid value!\n");


return;


}

-}



-/**


Set the boot bank to the default bank


*/

-void cpld_set_defbank(void)
-{

u8 val;

val = CPLD_DEFAULT_BANK;

CPLD_WRITE(global_reset, val);

-}



-#ifdef DEBUG
-static void cpld_dump_regs(void)
-{

printf("chip_id1	= 0x%02x\n", CPLD_READ(chip_id1));
printf("chip_id2	= 0x%02x\n", CPLD_READ(chip_id2));
printf("sw_maj_ver	= 0x%02x\n", CPLD_READ(sw_maj_ver));
printf("sw_min_ver	= 0x%02x\n", CPLD_READ(sw_min_ver));
printf("hw_ver		= 0x%02x\n", CPLD_READ(hw_ver));
printf("software_on	= 0x%02x\n", CPLD_READ(software_on));
printf("cfg_rcw_src	= 0x%02x\n", CPLD_READ(cfg_rcw_src));
printf("res0		= 0x%02x\n", CPLD_READ(res0));
printf("vbank		= 0x%02x\n", CPLD_READ(vbank));
printf("sw1_sysclk	= 0x%02x\n", CPLD_READ(sw1_sysclk));
printf("sw2_status	= 0x%02x\n", CPLD_READ(sw2_status));
printf("sw3_status	= 0x%02x\n", CPLD_READ(sw3_status));
printf("sw4_status	= 0x%02x\n", CPLD_READ(sw4_status));
printf("sys_reset	= 0x%02x\n", CPLD_READ(sys_reset));
printf("global_reset	= 0x%02x\n", CPLD_READ(global_reset));
printf("res1		= 0x%02x\n", CPLD_READ(res1));
putc('\n');

-}
-#endif



-#ifndef CONFIG_SPL_BUILD
-int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{

int rc = 0;

if (argc <= 1)
return cmd_usage(cmdtp);



if (strcmp(argv[1], "reset") == 0) {
if (strcmp(argv[2], "altbank") == 0)


	cpld_set_altbank();


else


	cpld_set_defbank();



-#ifdef DEBUG

} else if (strcmp(argv[1], "dump") == 0) {
cpld_dump_regs();



-#endif

} else
rc = cmd_usage(cmdtp);



return rc;

-}



-U_BOOT_CMD(

cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
"Reset the board or alternate bank",
"reset - reset to default bank\n"
"cpld reset altbank - reset to alternate bank\n"

-#ifdef DEBUG

"cpld dump - display the CPLD registers\n"

-#endif

);

-#endif
diff --git a/board/freescale/t4rdb/cpld.h b/board/freescale/t4rdb/cpld.h
deleted file mode 100644
index dc3f9f3c26ca..000000000000
--- a/board/freescale/t4rdb/cpld.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/**


Copyright 2014 Freescale Semiconductor







Author: Chunhe Lan Chunhe.Lan@freescale.com







This file provides support for the ngPIXIS, a board-specific FPGA used on



some Freescale reference boards.


*/


-/*


CPLD register set. Feel free to add board-specific #ifdefs where necessary.


*/

-struct cpld_data {

u8 chip_id1;	/* 0x00 - CPLD Chip ID1 Register */
u8 chip_id2;	/* 0x01 - CPLD Chip ID2 Register */
u8 sw_maj_ver;	/* 0x02 - CPLD Code Major Version Register */
u8 sw_min_ver;	/* 0x03 - CPLD Code Minor Version Register */
u8 hw_ver;	/* 0x04 - PCBA Version Register */
u8 software_on;	/* 0x05 - Override Physical Switch Enable Register */
u8 cfg_rcw_src;	/* 0x06 - RCW Source Location Control Register */
u8 res0;	/* 0x07 - not used */
u8 vbank;	/* 0x08 - Flash Bank Selection Control Register */
u8 sw1_sysclk;	/* 0x09 - SW1 Status Read Back Register */
u8 sw2_status;	/* 0x0a - SW2 Status Read Back Register */
u8 sw3_status;	/* 0x0b - SW3 Status Read Back Register */
u8 sw4_status;	/* 0x0c - SW4 Status Read Back Register */
u8 sys_reset;	/* 0x0d - Reset System With Reserving Registers Value*/
u8 global_reset;/* 0x0e - Reset System With Default Registers Value */
u8 res1;	/* 0x0f - not used */

-};



-#define CPLD_BANK_SEL_MASK	0x07
-#define CPLD_BANK_SEL_EN	0x04
-#define CPLD_SYSTEM_RESET	0x01
-#define CPLD_SELECT_BANK0	0x00
-#define CPLD_SELECT_BANK4	0x04
-#define CPLD_DEFAULT_BANK	0x01



-/* Pointer to the CPLD register set */



-u8 cpld_read(unsigned int reg);
-void cpld_write(unsigned int reg, u8 value);



-#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
-#define CPLD_WRITE(reg, value) \

cpld_write(offsetof(struct cpld_data, reg), value)




diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c
deleted file mode 100644
index 57cbde154f0e..000000000000
--- a/board/freescale/t4rdb/ddr.c
+++ /dev/null
@@ -1,128 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*


Copyright 2014 Freescale Semiconductor, Inc.


*/


-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/global_data.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-#include "ddr.h"



-DECLARE_GLOBAL_DATA_PTR;



-void fsl_ddr_board_options(memctl_options_t *popts,

		dimm_params_t *pdimm,


		unsigned int ctrl_num)



-{

const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;

if (ctrl_num > 2) {
printf("Not supported controller number %d\n", ctrl_num);


return;


}
if (!pdimm->n_ranks)
return;



/*
* we use identical timing for all slots. If needed, change the code


* to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];


*/


if (popts->registered_dimm_en)
pbsp = rdimms[0];


else
pbsp = udimms[0];




/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.


*/


ddr_freq = get_ddr_freq(0) / 1000000;
while (pbsp->datarate_mhz_high) {
if (pbsp->n_ranks == pdimm->n_ranks &&


    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {


	if (ddr_freq <= pbsp->datarate_mhz_high) {


		popts->clk_adjust = pbsp->clk_adjust;


		popts->wrlvl_start = pbsp->wrlvl_start;


		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;


		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;


		goto found;


	}


	pbsp_highest = pbsp;


}


pbsp++;


}

if (pbsp_highest) {
printf("Error: board specific timing not found for data\n"


	"rate %lu MT/s\n"


	"Trying to use the highest speed (%u) parameters\n",


	ddr_freq, pbsp_highest->datarate_mhz_high);


popts->clk_adjust = pbsp_highest->clk_adjust;


popts->wrlvl_start = pbsp_highest->wrlvl_start;


popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;


popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;


} else {
panic("DIMM is not supported by this board");


}

-found:

debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x,\n"


"wrlvl_ctrl_3 0x%x\n",


pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,


pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,


pbsp->wrlvl_ctl_3);



/*
* Factors to consider for half-strength driver enable:


*	- number of DIMMs installed


*/


popts->half_strength_driver_enable = 0;
/*
* Write leveling override


*/


popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;

/*
* Rtt and Rtt_WR override


*/


popts->rtt_override = 0;

/* Enable ZQ calibration */
popts->zq_en = 1;

/* DHC_EN =1, ODT = 75 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN |

DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);

popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);

/* optimize cpo for erratum A-009942 */
popts->cpo_sample = 0x64;

-}



-int dram_init(void)
-{

phys_size_t dram_size;

puts("Initializing....using SPD\n");


-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)

dram_size = fsl_ddr_sdram();

-#else

/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();

-#endif

dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;

gd->ram_size = dram_size;

return 0;

-}
diff --git a/board/freescale/t4rdb/ddr.h b/board/freescale/t4rdb/ddr.h
deleted file mode 100644
index 74a277961144..000000000000
--- a/board/freescale/t4rdb/ddr.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*


Copyright 2014 Freescale Semiconductor, Inc.


*/


-#ifndef __DDR_H__
-#define __DDR_H__
-struct board_specific_parameters {

u32 n_ranks;
u32 datarate_mhz_high;
u32 rank_gb;
u32 clk_adjust;
u32 wrlvl_start;
u32 wrlvl_ctl_2;
u32 wrlvl_ctl_3;

-};



-/*


These tables contain all valid speeds we want to override with board



specific parameters. datarate_mhz_high values need to be in ascending



order


for each n_ranks group.


*/

-static const struct board_specific_parameters udimm0[] = {

/*
* memory controller 0


*   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl


* ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3


*/


{2,  1350, 4,  8,     8, 0x0809090b, 0x0c0c0d0a},
{2,  1350, 0, 10,     7, 0x0709090b, 0x0c0c0d09},
{2,  1666, 4,  8,     8, 0x080a0a0d, 0x0d10100b},
{2,  1666, 0, 10,     7, 0x080a0a0c, 0x0d0d0e0a},
{2,  1900, 0,  8,     8, 0x090a0b0e, 0x0f11120c},
{2,  2140, 0,  8,     8, 0x090a0b0e, 0x0f11120c},
{1,  1350, 0, 10,     8, 0x0809090b, 0x0c0c0d0a},
{1,  1700, 0, 10,     8, 0x080a0a0c, 0x0c0d0e0a},
{1,  1900, 0,  8,     8, 0x080a0a0c, 0x0e0e0f0a},
{1,  2140, 0,  8,     8, 0x090a0b0c, 0x0e0f100b},
{}

-};



-static const struct board_specific_parameters rdimm0[] = {

/*
* memory controller 0


*   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl


* ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3


*/


{4,  1350, 0, 10,     9, 0x08070605, 0x06070806},
{4,  1666, 0, 10,    11, 0x0a080706, 0x07090906},
{4,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
{2,  1350, 0, 10,     9, 0x08070605, 0x06070806},
{2,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
{2,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
{1,  1350, 0, 10,     9, 0x08070605, 0x06070806},
{1,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
{1,  2140, 0,  8,    12, 0x0b090807, 0x080a0b07},
{}

-};



-/*


The three slots have slightly different timing. The center values are good



for all slots. We use identical speed tables for them. In future use, if



DIMMs require separated tables, make more entries as needed.


*/

-static const struct board_specific_parameters *udimms[] = {

udimm0,

-};



-/*


The three slots have slightly different timing. See comments above.


*/

-static const struct board_specific_parameters *rdimms[] = {

rdimm0,

-};




-#endif
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
deleted file mode 100644
index c815a3a4fa52..000000000000
--- a/board/freescale/t4rdb/eth.c
+++ /dev/null
@@ -1,152 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*


Copyright 2014 Freescale Semiconductor, Inc.







Chunhe Lan Chunhe.Lan@freescale.com


*/


-#include <common.h>
-#include <command.h>
-#include <fdt_support.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_dtsec.h>
-#include <asm/fsl_serdes.h>
-#include <hwconfig.h>



-#include "../common/fman.h"
-#include "t4rdb.h"



-void fdt_fixup_board_enet(void *fdt)
-{

return;

-}



-int board_eth_init(struct bd_info *bis)
-{
-#if defined(CONFIG_FMAN_ENET)

int i, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
struct mii_dev *dev;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_prtcl_s1, srds_prtcl_s2;

srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
		FSL_CORENET2_RCWSR4_SRDS1_PRTCL;


srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
		FSL_CORENET2_RCWSR4_SRDS2_PRTCL;


srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;

dtsec_mdio_info.regs =
(struct memac_mdio_controller



*)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;


dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;

/* Register the 1G MDIO bus */
fm_memac_mdio_init(bis, &dtsec_mdio_info);

tgec_mdio_info.regs =
(struct memac_mdio_controller



*)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;

tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;

/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);

if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) {
/* SGMII */


fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);


fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);


fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3);


fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4);


} else {
puts("Invalid SerDes1 protocol for T4240RDB\n");


}

fm_disable_port(FM1_DTSEC5);
fm_disable_port(FM1_DTSEC6);

for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC;

i++) {

interface = fm_info_get_enet_if(i);


switch (interface) {


case PHY_INTERFACE_MODE_SGMII:


	dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);


	fm_info_set_mdio(i, dev);


	break;


default:


	break;


}


}

for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC;

i++) {

switch (fm_info_get_enet_if(i)) {


case PHY_INTERFACE_MODE_XGMII:


	dev =



miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);

	fm_info_set_mdio(i, dev);


	break;


default:


	break;


}


}


-#if (CONFIG_SYS_NUM_FMAN == 2)

if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
/* SGMII && XFI */


fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);


fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);


fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);


fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8);


fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);


fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);


fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR);


fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR);


} else {
puts("Invalid SerDes2 protocol for T4240RDB\n");


}

fm_disable_port(FM2_DTSEC5);
fm_disable_port(FM2_DTSEC6);
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC;

i++) {

interface = fm_info_get_enet_if(i);


switch (interface) {


case PHY_INTERFACE_MODE_SGMII:


	dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);


	fm_info_set_mdio(i, dev);


	break;


default:


	break;


}


}

for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC;

i++) {

switch (fm_info_get_enet_if(i)) {


case PHY_INTERFACE_MODE_XGMII:


	dev =



miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);

	fm_info_set_mdio(i, dev);


	break;


default:


	break;


}


}

-#endif /* CONFIG_SYS_NUM_FMAN */


cpu_eth_init(bis);

-#endif /* CONFIG_FMAN_ENET */


return pci_eth_init(bis);

-}
diff --git a/board/freescale/t4rdb/law.c b/board/freescale/t4rdb/law.c
deleted file mode 100644
index 038f60565f7e..000000000000
--- a/board/freescale/t4rdb/law.c
+++ /dev/null
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*


Copyright 2014 Freescale Semiconductor, Inc.


*/


-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>



-struct law_entry law_table[] = {

SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M,

LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS

SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M,

LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS

SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M,

LAW_TRGT_IF_QMAN),
-#endif
-#ifdef CONFIG_SYS_CPLD_BASE_PHYS

SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K,

LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS

/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M,

LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS

SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K,

LAW_TRGT_IF_IFC),
-#endif
-};



-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t4rdb/pci.c b/board/freescale/t4rdb/pci.c
deleted file mode 100644
index c2bc05164dd1..000000000000
--- a/board/freescale/t4rdb/pci.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*


Copyright 2014 Freescale Semiconductor, Inc.


*/


-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>



-#if !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{

fsl_pcie_init_board(0);

-}



-void pci_of_setup(void *blob, struct bd_info *bd)
-{

FT_FSL_PCI_SETUP;

-}
-#endif
diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c
deleted file mode 100644
index e2f9c9b3de29..000000000000
--- a/board/freescale/t4rdb/spl.c
+++ /dev/null
@@ -1,98 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*


Copyright 2015 Freescale Semiconductor, Inc.







Author: Chunhe Lan Chunhe.Lan@freescale.com


*/


-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env_internal.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/spl.h>
-#include <malloc.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <i2c.h>



-#include "t4rdb.h"



-#define FSL_CORENET_CCSR_PORSR1_RCW_MASK	0xFF800000



-DECLARE_GLOBAL_DATA_PTR;



-phys_size_t get_effective_memsize(void)
-{

return CONFIG_SYS_L3_SIZE;

-}



-unsigned long get_board_sys_clk(void)
-{

return CONFIG_SYS_CLK_FREQ;

-}



-unsigned long get_board_ddr_clk(void)
-{

return CONFIG_DDR_CLK_FREQ;

-}



-void board_init_f(ulong bootflag)
-{

u32 plat_ratio, sys_clk, ccb_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;

/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));

/* Update GD pointer */
gd = (gd_t *)(CONFIG_SPL_GD_ADDR);

/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("" : : : "memory");

console_init_f();

/* initialize selected port with appropriate baud rate */
sys_clk = get_board_sys_clk();
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;

ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
     ccb_clk / 16 / CONFIG_BAUDRATE);



puts("\nSD boot...\n");

relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t

*)CONFIG_SPL_GD_ADDR, 0x0);
-}



-void board_init_r(gd_t *gd, ulong dest_addr)
-{

struct bd_info *bd;

bd = (struct bd_info *)(gd + sizeof(gd_t));
memset(bd, 0, sizeof(struct bd_info));
gd->bd = bd;

arch_cpu_init();
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
	CONFIG_SPL_RELOC_MALLOC_SIZE);


gd->flags |= GD_FLG_FULL_MALLOC_INIT;

mmc_initialize(bd);
mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
	   (uchar *)SPL_ENV_ADDR);



gd->env_addr  = (ulong)(SPL_ENV_ADDR);
gd->env_valid = ENV_VALID;

i2c_init_all();

dram_init();

mmc_boot();

-}
diff --git a/board/freescale/t4rdb/t4240rdb.c
b/board/freescale/t4rdb/t4240rdb.c
deleted file mode 100644
index 6ab35ca9185b..000000000000
--- a/board/freescale/t4rdb/t4240rdb.c
+++ /dev/null
@@ -1,153 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*


Copyright 2014 Freescale Semiconductor, Inc.


*/


-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <netdev.h>
-#include <asm/global_data.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>



-#include "t4rdb.h"
-#include "cpld.h"
-#include "../common/vid.h"



-DECLARE_GLOBAL_DATA_PTR;



-int checkboard(void)
-{

struct cpu_type *cpu = gd->arch.cpu;
u8 sw;

printf("Board: %sRDB, ", cpu->name);
printf("Board rev: 0x%02x CPLD ver: 0x%02x%02x, ",
      CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver),



CPLD_READ(sw_min_ver));


sw = CPLD_READ(vbank);
sw = sw & CPLD_BANK_SEL_MASK;

if (sw <= 7)
printf("vBank: %d\n", sw);


else
printf("Unsupported Bank=%x\n", sw);



puts("SERDES Reference Clocks:\n");
printf("       SERDES1=100MHz SERDES2=156.25MHz\n"
      "       SERDES3=100MHz SERDES4=100MHz\n");



return 0;

-}



-int board_early_init_r(void)
-{

const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);

/*
* Remap Boot flash + PROMJET region to caching-inhibited


* so that flash can be erased properly.


*/



/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();

if (flash_esel == -1) {
/* very unlikely unless something is messed up */


puts("Error: Could not find TLB for FLASH BASE\n");


flash_esel = 2;	/* give our best effort to continue */


} else {
/* invalidate existing TLB entry for flash + promjet */


disable_tlb(flash_esel);


}

set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,


0, flash_esel, BOOKE_PAGESZ_256M, 1);



/*
* Adjust core voltage according to voltage ID


* This function changes I2C mux to channel 2.


*/
if (adjust_vdd(0))
printf("Warning: Adjusting core voltage failed.\n");



return 0;

-}



-int misc_init_r(void)
-{

return 0;

-}



-int ft_board_setup(void *blob, struct bd_info *bd)
-{

phys_addr_t base;
phys_size_t size;

ft_cpu_setup(blob, bd);

base = env_get_bootm_low();
size = env_get_bootm_size();

fdt_fixup_memory(blob, (u64)base, (u64)size);


-#ifdef CONFIG_PCI

pci_of_setup(blob, bd);

-#endif


fdt_fixup_liodn(blob);
fsl_fdt_fixup_dr_usb(blob, bd);


-#ifdef CONFIG_SYS_DPAA_FMAN
-#ifndef CONFIG_DM_ETH

fdt_fixup_fman_ethernet(blob);

-#endif

fdt_fixup_board_enet(blob);

-#endif


return 0;

-}



-/*


This function is called by bdinfo to print detail board information.



As an exmaple for future board, we organize the messages into



several sections. If applicable, the message is in the format of



<name>      = <value>



It should aligned with normal output of bdinfo command.







Voltage: Core, DDR and another configurable voltages



Clock  : Critical clocks which are not printed already



RCW    : RCW source if not printed already



Misc   : Other important information not in above catagories


*/

-void board_detail(void)
-{

int rcwsrc;

/* RCW section SW3[4] */
rcwsrc = 0x0;
puts("RCW source  = ");
switch (rcwsrc & 0x1) {
case 0x1:
puts("SDHC/eMMC\n");


break;


default:
puts("I2C normal addressing\n");


break;


}

-}
diff --git a/board/freescale/t4rdb/t4_pbi.cfg
b/board/freescale/t4rdb/t4_pbi.cfg
deleted file mode 100644
index 0b326fa1635a..000000000000
--- a/board/freescale/t4rdb/t4_pbi.cfg
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-# Copyright 2014 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#



-#PBI commands
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#512KB SRAM
-09010100 00000000
-09010104 fff80009
-09010f00 08000000
-#enable CPC1
-09010000 80000000
-#Configure LAW for CPC1
-09000d00 00000000
-09000d04 fff80000
-09000d08 81000012
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Flush PBL data
-091380c0 00100000
diff --git a/board/freescale/t4rdb/t4_sd_rcw.cfg
b/board/freescale/t4rdb/t4_sd_rcw.cfg
deleted file mode 100644
index cc2bff68269c..000000000000
--- a/board/freescale/t4rdb/t4_sd_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#serdes protocol  27_55_1_9
-16070019 18101916 00000000 00000000
-6c6e0848 00448c00 6c020000 f5000000
-00000000 ee0000ee 00000000 000307fc
-00000000 00000000 00000000 00000028
diff --git a/board/freescale/t4rdb/t4rdb.h b/board/freescale/t4rdb/t4rdb.h
deleted file mode 100644
index 3f1fa7bbd24e..000000000000
--- a/board/freescale/t4rdb/t4rdb.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*


Copyright 2014 Freescale Semiconductor, Inc.


*/


-#ifndef __T4RDB_H__
-#define __T4RDB_H__



-#undef CONFIG_SYS_NUM_FM1_DTSEC
-#undef CONFIG_SYS_NUM_FM2_DTSEC
-#define CONFIG_SYS_NUM_FM1_DTSEC	4
-#define CONFIG_SYS_NUM_FM2_DTSEC	4



-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, struct bd_info *bd);



-#endif
diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c
deleted file mode 100644
index b927dd8484f8..000000000000
--- a/board/freescale/t4rdb/tlb.c
+++ /dev/null
@@ -1,123 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*


Copyright 2014 Freescale Semiconductor, Inc.


*/


-#include <common.h>
-#include <asm/mmu.h>



-struct fsl_e_tlb_entry tlb_table[] = {

/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
      CONFIG_SYS_INIT_RAM_ADDR_PHYS,


      MAS3_SX|MAS3_SW|MAS3_SR, 0,


      0, 0, BOOKE_PAGESZ_4K, 0),


SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,


      MAS3_SX|MAS3_SW|MAS3_SR, 0,


      0, 0, BOOKE_PAGESZ_4K, 0),


SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,


      MAS3_SX|MAS3_SW|MAS3_SR, 0,


      0, 0, BOOKE_PAGESZ_4K, 0),


SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,


      MAS3_SX|MAS3_SW|MAS3_SR, 0,


      0, 0, BOOKE_PAGESZ_4K, 0),



/* TLB 1 */
/* *I*** - Covers boot page */

-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)

/*
* *I*G - L3SRAM. When L3 is used as 512K SRAM */


SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR,

CONFIG_SYS_INIT_L3_ADDR,

      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,


	0, 0, BOOKE_PAGESZ_512K, 1),



-#else

SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,


      0, 0, BOOKE_PAGESZ_4K, 1),



-#endif


/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,


      0, 1, BOOKE_PAGESZ_16M, 1),



/* *I*G* - Flash, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE,

CONFIG_SYS_FLASH_BASE_PHYS,

      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,


      0, 2, BOOKE_PAGESZ_256M, 1),




-#ifndef CONFIG_SPL_BUILD

/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT,

CONFIG_SYS_PCIE1_MEM_PHYS,

      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,


      0, 3, BOOKE_PAGESZ_1G, 1),



/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
      CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,


      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,


      0, 4, BOOKE_PAGESZ_256M, 1),



SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
      CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,


      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,


      0, 5, BOOKE_PAGESZ_256M, 1),



/* *I*G* - PCI I/O */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT,

CONFIG_SYS_PCIE1_IO_PHYS,

      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,


      0, 6, BOOKE_PAGESZ_256K, 1),



/* Bman/Qman */

-#ifdef CONFIG_SYS_BMAN_MEM_PHYS

SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE,

CONFIG_SYS_BMAN_MEM_PHYS,

      MAS3_SX|MAS3_SW|MAS3_SR, 0,


      0, 9, BOOKE_PAGESZ_16M, 1),


SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,


      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,


      0, 10, BOOKE_PAGESZ_16M, 1),



-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS

SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE,

CONFIG_SYS_QMAN_MEM_PHYS,

      MAS3_SX|MAS3_SW|MAS3_SR, 0,


      0, 11, BOOKE_PAGESZ_16M, 1),


SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,


      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,


      0, 12, BOOKE_PAGESZ_16M, 1),



-#endif
-#endif



-#ifdef CONFIG_SYS_DCSRBAR_PHYS

SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,


      0, 13, BOOKE_PAGESZ_32M, 1),



-#endif
-#ifdef CONFIG_SYS_NAND_BASE

/*
* *I*G - NAND


* entry 14 and 15 has been used hard coded, they will be disabled


* in cpu_init_f, so we use entry 16 for nand.


*/


SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE,

CONFIG_SYS_NAND_BASE_PHYS,

      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,


      0, 16, BOOKE_PAGESZ_64K, 1),



-#endif
-#ifdef CONFIG_SYS_CPLD_BASE

SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE,

CONFIG_SYS_CPLD_BASE_PHYS,

      MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,


      0, 17, BOOKE_PAGESZ_4K, 1),



-#endif
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)

SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,

CONFIG_SYS_DDR_SDRAM_BASE,

      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,


      0, 18, BOOKE_PAGESZ_2G, 1)



-#endif
-};



-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig
deleted file mode 100644
index 706d6a2367d5..000000000000
--- a/configs/T4160RDB_defconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4160RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_CORTINA=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T4240RDB_SDCARD_defconfig
b/configs/T4240RDB_SDCARD_defconfig
deleted file mode 100644
index 61670fa3d14d..000000000000
--- a/configs/T4240RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,78 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_CORTINA=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
deleted file mode 100644
index 2c8a2f0ef271..000000000000
--- a/configs/T4240RDB_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_CORTINA=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index 8b480dfd6901..19c26572ddcc 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -46,8 +46,7 @@ config SYS_NUM_DDR_CTLRS
   		ARCH_P4080	|| \
   		ARCH_P5040	|| \
   		ARCH_LX2160A	|| \

	ARCH_LX2162A	|| \


	ARCH_T4160




	ARCH_LX2162A

default 1

config SYS_FSL_DDR_VER
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 4ff35c4df591..80bf3db50d02 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -713,7 +713,6 @@ config SYS_DPAA_QBMAN
   	     ARCH_T1042 || \
   	     ARCH_T2080 || \
   	     ARCH_T4240 || \

     ARCH_T4160 || \
ARCH_P4080 || \
ARCH_P3041 || \
ARCH_P5040 || \



diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index c988e4e9257f..ae3841217663 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -26,7 +26,6 @@ obj-$(CONFIG_ARCH_T1042)	+= t1040.o
 obj-$(CONFIG_ARCH_T1024) += t1024.o
 obj-$(CONFIG_ARCH_T2080) += t2080.o
 obj-$(CONFIG_ARCH_T4240) += t4240.o
-obj-$(CONFIG_ARCH_T4160) += t4240.o
 obj-$(CONFIG_ARCH_B4420) += b4860.o
 obj-$(CONFIG_ARCH_B4860) += b4860.o
 obj-$(CONFIG_ARCH_LS1043A)	+= ls1043.o
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
deleted file mode 100644
index 7f831fb8bca5..000000000000
--- a/include/configs/T4240RDB.h
+++ /dev/null
@@ -1,667 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*


Copyright 2014 Freescale Semiconductor, Inc.



Copyright 2020 NXP


*/


-/*


T4240 RDB board configuration file


*/

-#ifndef __CONFIG_H
-#define __CONFIG_H



-#include <linux/stringify.h>



-#define CONFIG_FSL_SATA_V2
-#define CONFIG_PCIE4



-#define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq
*/



-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI
$(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
-#ifndef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
-#else
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_PAD_TO		0x40000
-#define CONFIG_SPL_MAX_SIZE		0x28000
-#define RESET_VECTOR_OFFSET		0x27FFC
-#define BOOT_PAGE_OFFSET		0x27000



-#ifdef	CONFIG_SDCARD
-#define CONFIG_RESET_VECTOR_ADDRESS	0x200FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST	0x00200000
-#define CONFIG_SYS_MMC_U_BOOT_START	0x00200000
-#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#endif
-#define CONFIG_SYS_FSL_PBL_RCW
$(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
-#endif



-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_SKIP_RELOCATE
-#define CONFIG_SPL_COMMON_INIT_DDR
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif



-#endif
-#endif /* CONFIG_RAMBOOT_PBL */



-#define CONFIG_DDR_ECC



-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */



-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
-#endif



-#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1			/* PCIE controller 1 */
-#define CONFIG_PCIE2			/* PCIE controller 2 */
-#define CONFIG_PCIE3			/* PCIE controller 3 */
-#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */



-/*


These can be toggled for performance analysis, otherwise use default.


*/

-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BTB			/* toggle branch predition */
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
-#endif



-#define CONFIG_ENABLE_36BIT_PHYS



-/*


Config the L3 Cache as L3 SRAM


*/

-#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
-#define CONFIG_SYS_L3_SIZE		(512 << 10)
-#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 *
1024)
-#define SPL_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12






-#define CONFIG_SPL_RELOC_MALLOC_SIZE	(50 << 10)
-#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 *
1024)



-#define CONFIG_SYS_DCSRBAR		0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull



-/*


DDR Setup


*/

-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE



-#define CONFIG_DIMM_SLOTS_PER_CTLR	1
-#define CONFIG_CHIP_SELECTS_PER_CTRL	4



-#define CONFIG_DDR_SPD



-/*


IFC Definitions


*/

-#define CONFIG_SYS_FLASH_BASE	0xe0000000
-#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull |
CONFIG_SYS_FLASH_BASE)



-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-#endif



-#define CONFIG_HWCONFIG



-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address
*/
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \

((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)



-#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000



-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \

			GENERATED_GBL_DATA_SIZE)



-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET



-#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)



-/* Serial Port - controlled on board with jumper J8


open - index 2



shorted - index 1


*/

-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)



-#define CONFIG_SYS_BAUDRATE_TABLE	\

{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}


-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)



-/* I2C */
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
-#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
-#endif



-#define CONFIG_SYS_I2C_FSL



-/*


General PCI



Memory space is mapped 1-1, but I/O space must start from 0.


*/


-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull



-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull



-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
-#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull



-/* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
-#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull



-#ifdef CONFIG_PCI
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif



-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#endif	/* CONFIG_PCI */



-/* SATA */
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE	2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA



-#define CONFIG_LBA48
-#endif



-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_ETHPRIME		"FM1@DTSEC1"
-#endif



-/*


Environment


*/

-#define CONFIG_LOADS_ECHO		/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */



-/*


Miscellaneous configurable options


*/

-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address
*/



-/*


For booting Linux, the board info and command line data



have to be in the first 64 MB of memory, since this is



the maximum mapped by the Linux kernel during initialization.


*/

-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip
size */



-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial
port */
-#endif



-/*


Environment Configuration


*/

-#define CONFIG_ROOTPATH		"/opt/nfsroot"
-#define CONFIG_BOOTFILE		"uImage"
-#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP
server*/



-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR		1000000



-#define CONFIG_HVBOOT					\

"setenv bootargs config-addr=0x60000000; "	\
"bootm 0x01000000 - 0x00f00000"


-#define CONFIG_SYS_CLK_FREQ	66666666
-#define CONFIG_DDR_CLK_FREQ	133333333



-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
-#endif



-/*


DDR Setup


*/

-#define CONFIG_SYS_SPD_BUS_NUM	0
-#define SPD_EEPROM_ADDRESS1	0x52
-#define SPD_EEPROM_ADDRESS2	0x54
-#define SPD_EEPROM_ADDRESS3	0x56
-#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for
p3041/p5010 */
-#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */



-/*


IFC Definitions


*/

-#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NOR0_CSPR
   (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \

		+ 0x8000000) | \


		CSPR_PORT_SIZE_16 | \


		CSPR_MSEL_NOR | \


		CSPR_V)



-#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NOR1_CSPR
   (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \

		CSPR_PORT_SIZE_16 | \


		CSPR_MSEL_NOR | \


		CSPR_V)



-#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80



-#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \

		FTIM0_NOR_TEADC(0x5) | \


		FTIM0_NOR_TEAHC(0x5))



-#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \

		FTIM1_NOR_TRAD_NOR(0x1A) |\


		FTIM1_NOR_TSEQRAD_NOR(0x13))



-#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \

		FTIM2_NOR_TCH(0x4) | \


		FTIM2_NOR_TWPH(0x0E) | \


		FTIM2_NOR_TWP(0x1c))



-#define CONFIG_SYS_NOR_FTIM3	0x0



-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1
*/



-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout
(ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms)
*/



-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS
\

			+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}




-/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_MAX_ECCPOS	256
-#define CONFIG_SYS_NAND_MAX_OOBFREE	2
-#define CONFIG_SYS_NAND_BASE		0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull |
CONFIG_SYS_NAND_BASE)



-#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NAND_CSPR
   (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \

		| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \


		| CSPR_MSEL_NAND	/* MSEL = NAND */ \


		| CSPR_V)



-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)



-#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC
on encode */ \

		| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \


		| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \


		| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \


		| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \


		| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \


		| CSOR_NAND_PB(128))	/*Page Per Block = 128*/




-#define CONFIG_SYS_NAND_ONFI_DETECTION



-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \

			FTIM0_NAND_TWP(0x18)   | \


			FTIM0_NAND_TWCHT(0x07) | \


			FTIM0_NAND_TWH(0x0a))



-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \

			FTIM1_NAND_TWBE(0x39)  | \


			FTIM1_NAND_TRR(0x0e)   | \


			FTIM1_NAND_TRP(0x18))



-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \

			FTIM2_NAND_TREH(0x0a) | \


			FTIM2_NAND_TWHRE(0x1e))



-#define CONFIG_SYS_NAND_FTIM3		0x0



-#define CONFIG_SYS_NAND_DDR_LAW		11
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE	1



-#define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)



-#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
-#endif
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3



-/* CPLD on IFC */
-#define CONFIG_SYS_CPLD_BASE	0xffdf0000
-#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull |
CONFIG_SYS_CPLD_BASE)
-#define CONFIG_SYS_CSPR3_EXT	(0xf)
-#define CONFIG_SYS_CSPR3
   (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \

		| CSPR_PORT_SIZE_8 \


		| CSPR_MSEL_GPCM \


		| CSPR_V)




-#define CONFIG_SYS_AMASK3	IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3	0x0



-/* CPLD Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \

			FTIM0_GPCM_TEADC(0x0e) | \


			FTIM0_GPCM_TEAHC(0x0e))



-#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \

			FTIM1_GPCM_TRAD(0x1f))



-#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \

			FTIM2_GPCM_TCH(0x8) | \


			FTIM2_GPCM_TWP(0x1f))



-#define CONFIG_SYS_CS3_FTIM3		0x0



-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif



-/* I2C */
-#define CONFIG_SYS_FSL_I2C_SPEED	100000	/* I2C speed */
-#define CONFIG_SYS_FSL_I2C2_SPEED	100000	/* I2C2 speed */
-#define I2C_MUX_PCA_ADDR_PRI		0x77 /* I2C bus
multiplexer,primary */
-#define I2C_MUX_PCA_ADDR_SEC		0x76 /* I2C bus
multiplexer,secondary */



-#define I2C_MUX_CH_DEFAULT	0x8
-#define I2C_MUX_CH_VOL_MONITOR	0xa
-#define I2C_MUX_CH_VSC3316_FS	0xc
-#define I2C_MUX_CH_VSC3316_BS	0xd



-/* Voltage monitor on channel 2*/
-#define I2C_VOL_MONITOR_ADDR		0x40
-#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
-#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
-#define I2C_VOL_MONITOR_BUS_V_SHIFT	3



-#define CONFIG_VID_FLS_ENV		"t4240rdb_vdd_mv"
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_VID
-#endif
-#define CONFIG_VOL_MONITOR_IR36021_SET
-#define CONFIG_VOL_MONITOR_IR36021_READ
-/* The lowest and highest voltage allowed for T4240RDB */
-#define VDD_MV_MIN			819
-#define VDD_MV_MAX			1212



-/*


eSPI - Enhanced SPI


*/


-/* Qman/Bman */
-#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS	50
-#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE
CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE
(CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE
(CONFIG_SYS_BMAN_MEM_BASE + \

			CONFIG_SYS_BMAN_CENA_SIZE)



-#define CONFIG_SYS_BMAN_CINH_SIZE
(CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS	50
-#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE
CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE
(CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE
(CONFIG_SYS_QMAN_MEM_BASE + \

			CONFIG_SYS_QMAN_CENA_SIZE)



-#define CONFIG_SYS_QMAN_CINH_SIZE
(CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08



-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-#define CONFIG_SYS_PMAN
-#define CONFIG_SYS_DPAA_DCE
-#define CONFIG_SYS_DPAA_RMAN
-#define CONFIG_SYS_INTERLAKEN



-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*


env is stored at 0x100000, sector size is 0x10000, ucode is stored after



env, so we got 0x110000.


*/

-#define CONFIG_SYS_FMAN_FW_ADDR	0x110000
-#elif defined(CONFIG_SDCARD)
-/*


PBL SD boot image should stored at 0x1000(8 blocks), the size of the image



is


about 1MB (2048 blocks), Env is stored after the image, and the env size is



0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.


*/

-#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 0x820)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR	(8 *
CONFIG_SYS_NAND_BLOCK_SIZE)
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
-#define CONFIG_SYS_FDT_PAD		(0x3000 +
CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#endif /* CONFIG_NOBQFMAN */



-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_CORTINA_FW_ADDR		0xefe00000
-#define CONFIG_CORTINA_FW_LENGTH	0x40000
-#define SGMII_PHY_ADDR1 0x0
-#define SGMII_PHY_ADDR2 0x1
-#define SGMII_PHY_ADDR3 0x2
-#define SGMII_PHY_ADDR4 0x3
-#define SGMII_PHY_ADDR5 0x4
-#define SGMII_PHY_ADDR6 0x5
-#define SGMII_PHY_ADDR7 0x6
-#define SGMII_PHY_ADDR8 0x7
-#define FM1_10GEC1_PHY_ADDR	0x10
-#define FM1_10GEC2_PHY_ADDR	0x11
-#define FM2_10GEC1_PHY_ADDR	0x12
-#define FM2_10GEC2_PHY_ADDR	0x13
-#define CORTINA_PHY_ADDR1	FM1_10GEC1_PHY_ADDR
-#define CORTINA_PHY_ADDR2	FM1_10GEC2_PHY_ADDR
-#define CORTINA_PHY_ADDR3	FM2_10GEC1_PHY_ADDR
-#define CORTINA_PHY_ADDR4	FM2_10GEC2_PHY_ADDR
-#endif



-/* SATA */
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE	2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA



-#define CONFIG_LBA48
-#endif



-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_ETHPRIME		"FM1@DTSEC1"
-#endif



-/*
-* USB
-*/
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_HAS_FSL_DR_USB



-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR
CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif




-#define __USB_PHY_TYPE	utmi



-/*


T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be



3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to



2-way


interleaving. It can be cacheline, page, bank, superbank.



See doc/README.fsl-ddr for details.


*/

-#ifdef CONFIG_ARCH_T4240
-#define CTRL_INTLV_PREFERED 3way_4KB
-#else
-#define CTRL_INTLV_PREFERED cacheline
-#endif



-#define	CONFIG_EXTRA_ENV_SETTINGS				\

"hwconfig=fsl_ddr:"					\
"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
"bank_intlv=auto;"					\
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0"						\
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
"tftpflash=tftpboot $loadaddr $uboot && "		\
"protect off $ubootaddr +$filesize && "			\
"erase $ubootaddr +$filesize && "			\
"cp.b $loadaddr $ubootaddr $filesize && "		\
"protect on $ubootaddr +$filesize && "			\
"cmp.b $loadaddr $ubootaddr $filesize\0"		\
"consoledev=ttyS0\0"					\
"ramdiskaddr=2000000\0"					\
"ramdiskfile=t4240rdb/ramdisk.uboot\0"			\
"fdtaddr=1e00000\0"					\
"fdtfile=t4240rdb/t4240rdb.dtb\0"			\
"bdev=sda3\0"


-#define CONFIG_HVBOOT					\

"setenv bootargs config-addr=0x60000000; "	\
"bootm 0x01000000 - 0x00f00000"


-#define CONFIG_LINUX					\

"setenv bootargs root=/dev/ram rw "		\
"console=$consoledev,$baudrate $othbootargs;"	\
"setenv ramdiskaddr 0x02000000;"		\
"setenv fdtaddr 0x00c00000;"			\
"setenv loadaddr 0x1000000;"			\
"bootm $loadaddr $ramdiskaddr $fdtaddr"


-#define CONFIG_HDBOOT					\

"setenv bootargs root=/dev/$bdev rw "		\
"console=$consoledev,$baudrate $othbootargs;"	\
"tftp $loadaddr $bootfile;"			\
"tftp $fdtaddr $fdtfile;"			\
"bootm $loadaddr - $fdtaddr"


-#define CONFIG_NFSBOOTCOMMAND			\

"setenv bootargs root=/dev/nfs rw "	\
"nfsroot=$serverip:$rootpath "		\
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;"	\
"tftp $loadaddr $bootfile;"		\
"tftp $fdtaddr $fdtfile;"		\
"bootm $loadaddr - $fdtaddr"


-#define CONFIG_RAMBOOTCOMMAND				\

"setenv bootargs root=/dev/ram rw "		\
"console=$consoledev,$baudrate $othbootargs;"	\
"tftp $ramdiskaddr $ramdiskfile;"		\
"tftp $loadaddr $bootfile;"			\
"tftp $fdtaddr $fdtfile;"			\
"bootm $loadaddr $ramdiskaddr $fdtaddr"


-#define CONFIG_BOOTCOMMAND		CONFIG_LINUX



-#include <asm/fsl_secure_boot.h>



-#endif	/* __CONFIG_H */
2.17.1

    

RE: [PATCH 56/57] ppc: Remove T4160RDB board

Y.b. Lu

-#endif /* __CONFIG_H */