This patch adds support for the Amlogic AXG SoC, which is very close from the Amlogic GXL SoCs with : - Same 4xCortex-A53 CPUs but clocked at 1.2GHZ max - DDR Interface limited to DDR4 16bit - The whole physical register address space has been moved to 0xfxxxxxxx - The pinctrl setup has changed - The clock tree is different enough to use a different driver
Signed-off-by: Jerome Brunet jbrunet@baylibre.com Signed-off-by: Neil Armstrong narmstrong@baylibre.com --- arch/arm/include/asm/arch-meson/axg.h | 51 ++++++++++++++++ arch/arm/mach-meson/Kconfig | 8 +++ arch/arm/mach-meson/Makefile | 1 + arch/arm/mach-meson/board-axg.c | 112 ++++++++++++++++++++++++++++++++++ include/configs/meson64.h | 5 ++ 5 files changed, 177 insertions(+) create mode 100644 arch/arm/include/asm/arch-meson/axg.h create mode 100644 arch/arm/mach-meson/board-axg.c
diff --git a/arch/arm/include/asm/arch-meson/axg.h b/arch/arm/include/asm/arch-meson/axg.h new file mode 100644 index 0000000..28a38b7 --- /dev/null +++ b/arch/arm/include/asm/arch-meson/axg.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 BayLibre, SAS + * Author: Neil Armstrong narmstrong@baylibre.com + */ + +#ifndef __AXG_H__ +#define __AXG_H__ + +#define AXG_AOBUS_BASE 0xff800000 +#define AXG_PERIPHS_BASE 0xff634400 +#define AXG_HIU_BASE 0xff63c000 +#define AXG_ETH_BASE 0xff3f0000 + +/* Always-On Peripherals registers */ +#define AXG_AO_ADDR(off) (AXG_AOBUS_BASE + ((off) << 2)) + +#define AXG_AO_SEC_GP_CFG0 AXG_AO_ADDR(0x90) +#define AXG_AO_SEC_GP_CFG3 AXG_AO_ADDR(0x93) +#define AXG_AO_SEC_GP_CFG4 AXG_AO_ADDR(0x94) +#define AXG_AO_SEC_GP_CFG5 AXG_AO_ADDR(0x95) + +#define AXG_AO_MEM_SIZE_MASK 0xFFFF0000 +#define AXG_AO_MEM_SIZE_SHIFT 16 +#define AXG_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 +#define AXG_AO_BL31_RSVMEM_SIZE_SHIFT 16 +#define AXG_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF + +/* Peripherals registers */ +#define AXG_PERIPHS_ADDR(off) (AXG_PERIPHS_BASE + ((off) << 2)) + +#define AXG_ETH_REG_0 AXG_PERIPHS_ADDR(0x50) +#define AXG_ETH_REG_1 AXG_PERIPHS_ADDR(0x51) + +#define AXG_ETH_REG_0_PHY_INTF_RGMII BIT(0) +#define AXG_ETH_REG_0_PHY_INTF_RMII BIT(2) +#define AXG_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) +#define AXG_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) +#define AXG_ETH_REG_0_PHY_CLK_EN BIT(10) +#define AXG_ETH_REG_0_INVERT_RMII_CLK BIT(11) +#define AXG_ETH_REG_0_CLK_EN BIT(12) + +/* HIU registers */ +#define AXG_HIU_ADDR(off) (AXG_HIU_BASE + ((off) << 2)) + +#define AXG_MEM_PD_REG_0 AXG_HIU_ADDR(0x40) + +/* Ethernet memory power domain */ +#define AXG_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) + +#endif /* __AXG_H__ */ diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index 6225417..7f217fa 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -6,6 +6,8 @@ config MESON64_COMMON select CLK select DM select DM_SERIAL + select SYSCON + select REGMAP imply CMD_DM
config MESON_GX @@ -34,6 +36,12 @@ config MESON_GXM help Select this if your SoC is an S912
+config MESON_AXG + bool "AXG" + select MESON64_COMMON + help + Select this if your SoC is an A113X/D + endchoice
config SYS_SOC diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile index 78345b4..b716e1a 100644 --- a/arch/arm/mach-meson/Makefile +++ b/arch/arm/mach-meson/Makefile @@ -4,3 +4,4 @@
obj-y += board-common.o sm.o obj-$(CONFIG_MESON_GX) += board-gx.o +obj-$(CONFIG_MESON_AXG) += board-axg.o diff --git a/arch/arm/mach-meson/board-axg.c b/arch/arm/mach-meson/board-axg.c new file mode 100644 index 0000000..014b25d --- /dev/null +++ b/arch/arm/mach-meson/board-axg.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Beniamino Galvani b.galvani@gmail.com + * (C) Copyright 2018 Neil Armstrong narmstrong@baylibre.com + */ + +#include <common.h> +#include <asm/arch/eth.h> +#include <asm/arch/axg.h> +#include <asm/arch/mem.h> +#include <asm/io.h> +#include <asm/armv8/mmu.h> +#include <linux/sizes.h> +#include <phy.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Configure the reserved memory zones exported by the secure registers + * into EFI and DTB reserved memory entries. + */ +void meson_init_reserved_memory(void *fdt) +{ + u64 bl31_size, bl31_start; + u64 bl32_size, bl32_start; + u32 reg; + + /* + * Get ARM Trusted Firmware reserved memory zones in : + * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0 + * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL + * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL + */ + reg = readl(AXG_AO_SEC_GP_CFG3); + + bl31_size = ((reg & AXG_AO_BL31_RSVMEM_SIZE_MASK) + >> AXG_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K; + bl32_size = (reg & AXG_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K; + + bl31_start = readl(AXG_AO_SEC_GP_CFG5); + bl32_start = readl(AXG_AO_SEC_GP_CFG4); + + /* Add BL31 reserved zone */ + if (bl31_start && bl31_size) + meson_board_add_reserved_memory(fdt, bl31_start, bl31_size); + + /* Add BL32 reserved zone */ + if (bl32_start && bl32_size) + meson_board_add_reserved_memory(fdt, bl32_start, bl32_size); +} + +phys_size_t get_effective_memsize(void) +{ + /* Size is reported in MiB, convert it in bytes */ + return ((readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_MEM_SIZE_MASK) + >> AXG_AO_MEM_SIZE_SHIFT) * SZ_1M; +} + +static struct mm_region axg_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xf0000000UL, + .phys = 0xf0000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = axg_mem_map; + +/* Configure the Ethernet MAC with the requested interface mode + * with some optional flags. + */ +void meson_eth_init(phy_interface_t mode, unsigned int flags) +{ + switch (mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* Set RGMII mode */ + setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII | + AXG_ETH_REG_0_TX_PHASE(1) | + AXG_ETH_REG_0_TX_RATIO(4) | + AXG_ETH_REG_0_PHY_CLK_EN | + AXG_ETH_REG_0_CLK_EN); + break; + + case PHY_INTERFACE_MODE_RMII: + /* Set RMII mode */ + out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII | + AXG_ETH_REG_0_INVERT_RMII_CLK | + AXG_ETH_REG_0_CLK_EN); + break; + + default: + printf("Invalid Ethernet interface mode\n"); + return; + } + + /* Enable power gate */ + clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK); +} diff --git a/include/configs/meson64.h b/include/configs/meson64.h index 80c883e..f961f43 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -8,8 +8,13 @@ #define __MESON64_CONFIG_H
/* Generic Interrupt Controller Definitions */ +#if defined(CONFIG_MESON_AXG) +#define GICD_BASE 0xffc01000 +#define GICC_BASE 0xffc02000 +#else /* MESON GXL and GXBB */ #define GICD_BASE 0xc4301000 #define GICC_BASE 0xc4302000 +#endif
#define CONFIG_CPU_ARMV8 #define CONFIG_REMAKE_ELF