This patch hacks some generic code used to allow the ARMv8 platform to specify if it is booting in Aarch32 mode.
Some ARMv8 CPUs can be run in Aarch32 mode as well as Aarch64. A good example of this is ARM's AEMv8 FVP model which models the ARMv8 architecture rather than a specific CPU core.
This patch is co-authored with Soby Mathew Soby.Mathew@arm.com.
Signed-off-by: Ryan Harkin ryan.harkin@linaro.org --- Makefile | 5 +++++ arch/arm/Kconfig | 6 ++++++ arch/arm/cpu/armv7/virt-v7.c | 2 ++ arch/arm/cpu/armv8/u-boot-spl.lds | 5 +++++ arch/arm/cpu/armv8/u-boot.lds | 5 +++++ arch/arm/include/asm/armv8/mmu.h | 5 +++++ 6 files changed, 28 insertions(+)
diff --git a/Makefile b/Makefile index 37cbcb2..b923ef7 100644 --- a/Makefile +++ b/Makefile @@ -1182,8 +1182,13 @@ u-boot-img-spl-at-end.bin: u-boot.img spl/u-boot-spl.bin FORCE # relocation). # FIXME refactor dts/Makefile to share target/arch detection u-boot.elf: u-boot.bin +ifeq ($(CONFIG_ARMV8_AARCH32),y) + @$(OBJCOPY) -B arm -I binary -O elf32-littlearm \ + $< u-boot-elf.o +else @$(OBJCOPY) -B aarch64 -I binary -O elf64-littleaarch64 \ $< u-boot-elf.o +endif @$(LD) u-boot-elf.o -o $@ \ --defsym=_start=$(CONFIG_SYS_TEXT_BASE) \ -Ttext=$(CONFIG_SYS_TEXT_BASE) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d7a9b11..6475a21 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -44,6 +44,12 @@ config CPU_ARM1176 select HAS_VBAR select SYS_CACHE_SHIFT_5
+ +config ARMV8_AARCH32 + bool "some help" + help + some better help + config CPU_V7 bool select HAS_VBAR diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index d33e5c6..b0f54e3 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -131,12 +131,14 @@ int armv7_init_nonsec(void) * ram, so need to relocate secure section before enabling other * cores. */ +#ifndef CONFIG_ARMV8_AARCH32 relocate_secure_section();
#ifndef CONFIG_ARMV7_PSCI smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1); smp_kick_all_cpus(); #endif +#endif
/* call the non-sec switching code on this CPU also */ secure_ram_addr(_nonsec_init)(); diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds index cc427c3..bddfbe6 100644 --- a/arch/arm/cpu/armv8/u-boot-spl.lds +++ b/arch/arm/cpu/armv8/u-boot-spl.lds @@ -17,8 +17,13 @@ MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+#ifdef CONFIG_ARMV8_AARCH32 +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +#else OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") OUTPUT_ARCH(aarch64) +#endif ENTRY(_start) SECTIONS { diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds index fd15ad5..0543458 100644 --- a/arch/arm/cpu/armv8/u-boot.lds +++ b/arch/arm/cpu/armv8/u-boot.lds @@ -8,8 +8,13 @@ * SPDX-License-Identifier: GPL-2.0+ */
+#ifdef CONFIG_ARMV8_AARCH32 +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +#else OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") OUTPUT_ARCH(aarch64) +#endif ENTRY(_start) SECTIONS { diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index aa0f3c4..755c517 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -77,8 +77,13 @@ #define PTE_BLOCK_INNER_SHARE (3 << 8) #define PTE_BLOCK_AF (1 << 10) #define PTE_BLOCK_NG (1 << 11) +#ifdef CONFIG_ARMV8_AARCH32 +#define PTE_BLOCK_PXN ((1ULL) << 53) +#define PTE_BLOCK_UXN ((1ULL) << 54) +#else #define PTE_BLOCK_PXN (UL(1) << 53) #define PTE_BLOCK_UXN (UL(1) << 54) +#endif
/* * AttrIndx[2:0]