From: Patrice Chotard patrice.chotard@st.com
Add missing timer node to enable timer5 for STM32F7 SoCs family
Signed-off-by: Patrice Chotard patrice.chotard@st.com --- arch/arm/dts/stm32f7-u-boot.dtsi | 8 ++++++++ arch/arm/dts/stm32f746.dtsi | 7 +++++++ 2 files changed, 15 insertions(+)
diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi index 9a9e4e5f3718..4a677192a2dd 100644 --- a/arch/arm/dts/stm32f7-u-boot.dtsi +++ b/arch/arm/dts/stm32f7-u-boot.dtsi @@ -1,3 +1,11 @@ +/{ + soc { + timer5: timer@40000c00 { + u-boot,dm-pre-reloc; + }; + }; +}; + &pinctrl { usart1_pins_a: usart1@0 { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index 46d148eab2c8..8c6fa133e0ab 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -323,6 +323,13 @@ pinctrl-names = "default", "opendrain"; max-frequency = <48000000>; }; + + timer5: timer@40000c00 { + compatible = "st,stm32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <50>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; + }; }; };