26 Oct
2019
26 Oct
'19
2:06 a.m.
On Mon, Oct 07, 2019 at 02:04:27PM +0530, Lokesh Vutla wrote:
From: James Doublesin doublesin@ti.com
Added the following registers to the DDR configuration:
- ACIOCR0,
- ACIOCR3,
- V2H_CTL_REG,
- DX8SLxDQSCTL.
Modified enable_dqs_pd and disable_dqs_pd to only touch the associated bit fields for pullup and pulldown registers (to preserve slew rate and other bits in that same register). Also update the dts files in the same patch to maintain git bisectability.
Signed-off-by: James Doublesin doublesin@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Applied to u-boot/master, thanks!
--
Tom