According to the errata, some bits of an undocumented register in the DCSR must be set for every core in order to avoid a possible data or instruction corruption.
This is required for the 2.0 revision of the P2041 that should be used as soon as available in our design.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com ---
board/keymile/kmp204x/pbi.cfg | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/board/keymile/kmp204x/pbi.cfg b/board/keymile/kmp204x/pbi.cfg index f38dcf9..9af8bd5 100644 --- a/board/keymile/kmp204x/pbi.cfg +++ b/board/keymile/kmp204x/pbi.cfg @@ -8,6 +8,16 @@ #
#PBI commands +#Workaround for A-006559 needed for rev 2.0 of P2041 silicon +#Freescale's errarta sheet suggests it may be done with PBI +09000010 00000000 +09000014 00000000 +09000018 81d00000 +09021008 0000f000 +09021028 0000f000 +09021048 0000f000 +09021068 0000f000 +09000018 00000000 #Initialize CPC1 as 1MB SRAM 09010000 00200400 09138000 00000000