Re: [U-Boot] [PATCHv1] mx53ppd: Change UART clock divider for high baudrate

18 Feb 2018


      Hi Rick,
On Sat, Feb 17, 2018 at 9:24 PM, Rick Bronson rick@efn.org wrote:
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It would be nice to explain a bit how you achieve the higher baud rates.
Background: PLL2 runs at 400 MHz, PLL3 runs at 216 MHz.  One of
these PLL's are fed to a UART divider, the output of which sets the
maximum UART baud rates that are based on these rates divided by 16.
Before patch: PLL3 (400 MHz) for UART's, divide by 6, get 66.66 MHz
from it.  Max baud rate is 4.166 MBaud.
After patch: PLL2 (216 MHz), divide by 1, get 216 MHz from it.  Max
baud rate is 13.5 MBaud.
Thanks for the clarification.
Maybe Sebastian can send a v2 with this explanation incorporated.
Regards,
Fabio Estevam