Hello,
On Mon, 2020-05-04 at 16:32 +0200, Marek Vasut wrote:
On 5/4/20 4:27 PM, Fabio Estevam wrote:
Hi,
On Wed, Apr 29, 2020 at 10:05 AM Harald Seiler hws@denx.de wrote:
From: Marek Vasut marex@denx.de
Board files should not re-implement do_reset() to work around this function not being defined in for specific configurations. Rather, the fix is to compile in drivers which implement this properly. This patch enables sysreset and watchdog drivers in SPL and ties them together to implement the same as the do_reset() hack in the board file, except correctly in the DM/DT framework.
Signed-off-by: Marek Vasut marex@denx.de Cc: Fabio Estevam festevam@gmail.com Cc: Flavio Suligoi f.suligoi@asem.it Cc: Harald Seiler hws@denx.de Cc: Igor Opaniuk igor.opaniuk@toradex.com Cc: Marcel Ziswiler marcel.ziswiler@toradex.com Cc: Oleksandr Suvorov oleksandr.suvorov@toradex.com Cc: Peng Fan peng.fan@nxp.com Cc: Stefano Babic sbabic@denx.de
I noticed that this patch breaks the boot on i.MX8MP EVK. Only the following line is printed on boot:
U-Boot SPL 2020.07-rc1-00014-g8142a97d54 (May 04 2020 - 11:15:50 -0300)
If I revert this patch I can boot it again:
U-Boot SPL 2020.07-rc1-00015-g02cd8db94f (May 04 2020 - 11:17:25 -0300) Normal Boot Failed to find clock node. Check device tree WDT: Not found! Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0
U-Boot 2020.07-rc1-00015-g02cd8db94f (May 04 2020 - 11:17:25 -0300)
CPU: Freescale i.MX8MP rev1.0 at 1000 MHz Reset cause: POR Model: NXP i.MX8MPlus EVK board DRAM: 6 GiB MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 u-boot=>
The "Failed to find clock node. Check device tree" looks suspicious.
The "WDT: not found!" is probably the root cause of your problem. Maybe the WDT driver fails to probe because it can't resolve it's clock phandle ("Failed to find clock node")? So maybe you need to fix your clock in SPL.
"Failed to find clock node. Check device tree" comes from spl_board_init() in board/freescale/imx8mp_evk/spl.c; line 56:
ret = uclass_get_device_by_name(UCLASS_CLK, "clock-controller@30380000", &dev);
I see that wdog1 references the same clock here:
arch/arm/dts/imx8mp.dtsi; line 222:
wdog1: watchdog@30280000 { compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; reg = <0x30280000 0x10000>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; status = "disabled"; };
So the two issues are very likely related. The relevant clock's node is also enabled for SPL so I think the driver might be missing here. Maybe you need to add
CONFIG_SPL_CLK_IMX8MP=y
to your defconfig?