Support the DDR mode at dw-mmc controller
Signed-off-by: Jaehoon Chung jh80.chung@samsung.com --- drivers/mmc/dw_mmc.c | 10 +++++++++- include/dwmmc.h | 3 +++ 2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index d45c15c..174cd3a 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -285,7 +285,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) static void dwmci_set_ios(struct mmc *mmc) { struct dwmci_host *host = (struct dwmci_host *)mmc->priv; - u32 ctype; + u32 ctype, regs;
debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock);
@@ -304,6 +304,14 @@ static void dwmci_set_ios(struct mmc *mmc)
dwmci_writel(host, DWMCI_CTYPE, ctype);
+ regs = dwmci_readl(host, DWMCI_UHS_REG); + if (mmc->card_caps & MMC_MODE_DDR_52MHz) + regs |= DWMCI_DDR_MODE; + else + regs &= DWMCI_DDR_MODE; + + dwmci_writel(host, DWMCI_UHS_REG, regs); + if (host->clksel) host->clksel(host); } diff --git a/include/dwmmc.h b/include/dwmmc.h index f391b63..45d191a 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -123,6 +123,9 @@ #define DWMCI_BMOD_IDMAC_FB (1 << 1) #define DWMCI_BMOD_IDMAC_EN (1 << 7)
+/* UHS register */ +#define DWMCI_DDR_MODE (1 << 16) + /* quirks */ #define DWMCI_QUIRK_DISABLE_SMU (1 << 0)