Jason Liu wrote:
The patch add header files to support the Freescale i.MX53 processor, setting definitions for internal registers.
Signed-off-by:Jason Liu r64343@freescale.com
arch/arm/include/asm/arch-mx53/asm-offsets.h | 52 ++ arch/arm/include/asm/arch-mx53/crm_regs.h | 708 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx53/imx-regs.h | 193 +++++++ 3 files changed, 953 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx53/asm-offsets.h b/arch/arm/include/asm/arch-mx53/asm-offsets.h
The only difference with arch-mx51/asm-offset.h is:
< #define CLKCTL_CCGR7 0x84 < #define CLKCTL_CMEOR 0x88 ---
#define CLKCTL_CMEOR 0x84
We do not need to introduce a newer file.
diff --git a/arch/arm/include/asm/arch-mx53/crm_regs.h b/arch/arm/include/asm/arch-mx53/crm_regs.h new file mode 100644 index 0000000..cd39055 +/* Define the bits in register CCR */ +#define MXC_CCM_CCR_COSC_EN (0x1 << 12)
In mx53 some more bits are defined. However, I have not found grepping the code where they are defined. I do not think we have to introduce constants we do not need.
And this file must be merged with arch-mx51/crm_regs.h
diff --git a/arch/arm/include/asm/arch-mx53/imx-regs.h b/arch/arm/include/asm/arch-mx53/imx-regs.h new file mode 100644 index 0000000..104fae4 +#define IRAM_BASE_ADDR 0xF8000000 /* internal ram */
This file must be merged with the mx51 counterparts, splitting values where is needed, as in this case. Something like:
#if defined(CONFIG_MX51) #define IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */ #elif define (CONFIG_MX53) #define IRAM_BASE_ADDR 0xF8000000 /* internal ram */ #else #error "MX5 CPU not supported" #endif