This is really only an approximation using the largest RAM address available in the tables. There may be areas which are marked as reserved which are actually at the end of RAM.
Signed-off-by: Gabe Black gabeblack@chromium.org --- arch/x86/cpu/coreboot/sdram.c | 18 +++++++++++++++++- 1 files changed, 17 insertions(+), 1 deletions(-)
diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index b56085a..b5b086b 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -24,12 +24,28 @@
#include <common.h> #include <asm/u-boot-x86.h> +#include <asm/global_data.h> +#include <asm/ic/coreboot/sysinfo.h> +#include <asm/ic/coreboot/tables.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init_f(void) { - gd->ram_size = 64*1024*1024; + int i; + phys_size_t ram_size = 0; + for (i = 0; i < lib_sysinfo.n_memranges; i++) { + unsigned long long end = \ + lib_sysinfo.memrange[i].base + + lib_sysinfo.memrange[i].size; + if (lib_sysinfo.memrange[i].type == CB_MEM_RAM && + end > ram_size) { + ram_size = end; + } + } + gd->ram_size = ram_size; + if (ram_size == 0) + return -1; return 0; }