On Sun, 23 Nov 2014 14:43:11 +0100 Hans de Goede hdegoede@redhat.com wrote:
It turns out that there is a too large spread between boards to handle this with a default value, turn this into Kconfig options, and set the values the factory images are using for the Colombus and Mele_M9 boards.
Note this changes the ZQ default when not overriden through defconfig from 120 to 123, as that is what most boards seem to actually use.
Signed-off-by: Hans de Goede hdegoede@redhat.com
0x7b (or 123 in the decimal) form is a default reset value in the hardware register (at least on A10/A13/A20 and also on TI Keystone2 hardware). So it indeed makes sense to have it as the default value for u-boot. And also very likely shows that whoever provided the DRAM configurations with this value, did not in fact bother to really configure ZQ to something meaningful :-)
In general, if we read the JEDEC booklets, then ZQ calibration is the feature, which allows to improve reliability and increase DRAM clock speeds. The DRAM clock speeds, which are well beyond what the Allwinner A31 boards seem to be using at the moment.
I hope that 0x78 value for ZQ on Mele M9 is really there for a reason, and not something like actually 0x7B that got misread from the printed documentation or from screen :-) As the DRAM clock speeds on A31 hardware seem to be really very low, I would suspect that almost any ZQ value would be probably good enough in practice.
For A10/A13/A20 hardware we actually have easy tools to measure DRAM reliability. These tools can help to pick good ZQ settings. Something similar may be potentially implemented for A31 too.