Re: [PATCH 1/2] imx: add imx8x capricorn giedi board

28 Dec 2019

Hi Anatolji,
I pick up the series, but CONFIG_ENV_OFFSET is not set and it cannot be
built. Could you add this define to defconfig and repost it ? - thanks !
Best regards,
Stefano
On 22/10/19 10:34, Anatolij Gustschin wrote:
...
Add support for i.MX8X based Capricorn Giedi SoM.
Supported interfaces: GPIO, ENET, eMMC, I2C, UART.
Console output:
U-Boot SPL 2019.10-00178-g6e34009eee (Oct 21 2019 - 18:16:42 +0200)
  Trying to boot from MMC1
  Load image from MMC/SD 0x3e000
U-Boot 2019.10-00178-g6e34009eee (Oct 21 2019 - 18:16:42 +0200) ##v01.07
CPU:   NXP i.MX8QXP RevB A35 at 1200 MHz at 24C
Model: Siemens Giedi
  Board: Capricorn
  Build: SCFW 65afe5f6, SECO-FW 9d71fd5b, ATF d6451cc
  Boot:  MMC0
  DRAM:  1022 MiB
  MMC:   FSL_SDHC: 0
  Loading Environment from MMC... OK
  In:    serial@5a080000
  Out:   serial@5a080000
  Err:   serial@5a080000
  Net:   eth1: ethernet@5b050000 [PRIME]
  Autobooting in 1 seconds, press "<Esc><Esc>" to stop
Signed-off-by: Anatolij Gustschin agust@denx.de
arch/arm/dts/Makefile                       |   3 +-
 arch/arm/dts/imx8-giedi.dts                 |  10 +
 arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi  | 133 +++++++++
 arch/arm/dts/imx8qxp-capricorn.dtsi         | 285 ++++++++++++++++++
 arch/arm/mach-imx/imx8/Kconfig              |   6 +
 board/siemens/capricorn/Kconfig             |  12 +
 board/siemens/capricorn/MAINTAINERS         |   9 +
 board/siemens/capricorn/Makefile            |  12 +
 board/siemens/capricorn/board.c             | 443 ++++++++++++++++++++++++++++
 board/siemens/capricorn/imximage.cfg        |  22 ++
 board/siemens/capricorn/spl.c               |  47 +++
 board/siemens/capricorn/uboot-container.cfg |  13 +
 board/siemens/common/factoryset.c           |   2 +
 configs/giedi_defconfig                     |  99 +++++++
 include/configs/capricorn-common.h          | 190 ++++++++++++
 include/configs/giedi.h                     |  19 ++
 include/configs/siemens-ccp-common.h        |  20 ++
 include/configs/siemens-env-common.h        | 202 +++++++++++++
 18 files changed, 1526 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/imx8-giedi.dts
 create mode 100644 arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx8qxp-capricorn.dtsi
 create mode 100644 board/siemens/capricorn/Kconfig
 create mode 100644 board/siemens/capricorn/MAINTAINERS
 create mode 100644 board/siemens/capricorn/Makefile
 create mode 100644 board/siemens/capricorn/board.c
 create mode 100644 board/siemens/capricorn/imximage.cfg
 create mode 100644 board/siemens/capricorn/spl.c
 create mode 100644 board/siemens/capricorn/uboot-container.cfg
 create mode 100644 configs/giedi_defconfig
 create mode 100644 include/configs/capricorn-common.h
 create mode 100644 include/configs/giedi.h
 create mode 100644 include/configs/siemens-ccp-common.h
 create mode 100644 include/configs/siemens-env-common.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3b8dc2f..669d99e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -647,7 +647,8 @@ dtb-$(CONFIG_ARCH_IMX8) += \
   fsl-imx8qm-apalis.dtb \
   fsl-imx8qm-mek.dtb \
   fsl-imx8qxp-colibri.dtb \

fsl-imx8qxp-mek.dtb


fsl-imx8qxp-mek.dtb \
imx8-giedi.dtb

dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \
   imx8mm-evk.dtb
diff --git a/arch/arm/dts/imx8-giedi.dts b/arch/arm/dts/imx8-giedi.dts
new file mode 100644
index 0000000..0dbfef2
--- /dev/null
+++ b/arch/arm/dts/imx8-giedi.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*


Copyright 2019 Siemens AG


*/


+#include "imx8qxp-capricorn.dtsi"



+/ {

model = "Siemens Giedi";

+};
diff --git a/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi b/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi
new file mode 100644
index 0000000..1cf58fc
--- /dev/null
+++ b/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*


Copyright 2019 Siemens AG


*/


+&{/imx8qx-pm} {


u-boot,dm-spl;

+};



+&mu {

u-boot,dm-spl;

+};



+&clk {

u-boot,dm-spl;

+};



+&iomuxc {

u-boot,dm-spl;

+};



+&pd_lsio {

u-boot,dm-spl;

+};



+&pd_lsio_gpio0 {

u-boot,dm-spl;

+};



+&pd_lsio_gpio1 {

u-boot,dm-spl;

+};



+&pd_lsio_gpio2 {

u-boot,dm-spl;

+};



+&pd_lsio_gpio3 {

u-boot,dm-spl;

+};



+&pd_lsio_gpio4 {

u-boot,dm-spl;

+};



+&pd_lsio_gpio5 {

u-boot,dm-spl;

+};



+&pd_lsio_gpio6 {

u-boot,dm-spl;

+};



+&pd_lsio_gpio7 {

u-boot,dm-spl;

+};



+&pd_dma {

u-boot,dm-spl;

+};



+&pd_dma_lpuart0 {

u-boot,dm-spl;

+};



+&pd_dma_lpuart2 {

u-boot,dm-spl;

+};



+&pd_conn {

u-boot,dm-spl;

+};



+&pd_conn_sdch0 {

u-boot,dm-spl;

+};



+&pd_conn_sdch1 {

u-boot,dm-spl;

+};



+&pd_conn_sdch2 {

u-boot,dm-spl;

+};



+&gpio0 {

u-boot,dm-spl;

+};



+&gpio1 {

u-boot,dm-spl;

+};



+&gpio2 {

u-boot,dm-spl;

+};



+&gpio3 {

u-boot,dm-spl;

+};



+&gpio4 {

u-boot,dm-spl;

+};



+&gpio5 {

u-boot,dm-spl;

+};



+&gpio6 {

u-boot,dm-spl;

+};



+&gpio7 {

u-boot,dm-spl;

+};



+&lpuart0 {

u-boot,dm-spl;

+};



+&lpuart2 {

u-boot,dm-spl;

+};



+&usdhc1 {

u-boot,dm-spl;

+};



+&usdhc2 {

u-boot,dm-spl;

+};
diff --git a/arch/arm/dts/imx8qxp-capricorn.dtsi b/arch/arm/dts/imx8qxp-capricorn.dtsi
new file mode 100644
index 0000000..db5653e
--- /dev/null
+++ b/arch/arm/dts/imx8qxp-capricorn.dtsi
@@ -0,0 +1,285 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*


Copyright 2017 NXP







Copyright 2019 Siemens AG






*/


+/dts-v1/;



+#include "fsl-imx8qxp.dtsi"
+#include "imx8qxp-capricorn-u-boot.dtsi"



+/ {

model = "Siemens Giedi";
compatible = "siemens,capricorn", "fsl,imx8qxp";

chosen {
bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200";


stdout-path = &lpuart2;


};

leds {
compatible = "gpio-leds";


pinctrl-names = "default";


pinctrl-0 = <&pinctrl_gpio_leds>;



run {


	label = "run";


	gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;


	default-state = "on";


};



flt {


	label = "flt";


	gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;


	default-state = "on";


};



svc {


	label = "svc";


	gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;


	default-state = "on";


};



com1_tx {


	label = "com1-tx";


	gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;


	default-state = "on";


};



com1_rx {


	label = "com1-rx";


	gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;


	default-state = "on";


};



com2_tx {


	label = "com2-tx";


	gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;


	default-state = "on";


};



com2_rx {


	label = "com2-rx";


	gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;


	default-state = "on";


};



cloud {


	label = "cloud";


	gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;


	default-state = "on";


};



wlan {


	label = "wlan";


	gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;


	default-state = "on";


};



dbg1 {


	label = "dbg1";


	gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;


	default-state = "on";


};



dbg2 {


	label = "dbg2";


	gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;


	default-state = "on";


};



dbg3 {


	label = "dbg3";


	gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;


	default-state = "on";


};



dbg4 {


	label = "dbg4";


	gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;


	default-state = "on";


};


};

+};



+&iomuxc {

pinctrl-names = "default";

muxcgrp: imx8qxp-som {
pinctrl_gpio_leds: gpioledsgrp {


	fsl,pins = <


	SC_P_ESAI0_FST_LSIO_GPIO0_IO01		0x06000021


	SC_P_ESAI0_TX0_LSIO_GPIO0_IO04		0x06000021


	SC_P_SAI0_TXC_LSIO_GPIO0_IO26		0x06000021


	SC_P_SAI1_RXD_LSIO_GPIO0_IO29		0x06000021


	SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17	0x06000021


	SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18	0x06000021


	SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17	0x06000021


	SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18	0x06000021


	SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19	0x06000021


	SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x06000021


	SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00	0x06000021


	SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x06000021


	SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09	0x06000021


	>;


};



pinctrl_lpi2c0: lpi2c0grp {


	fsl,pins = <


	SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL	0x0C000020


	SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA	0x0C000020


	>;


};



pinctrl_lpi2c1: lpi2c1grp {


	fsl,pins = <


	SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL	0x0C000020


	SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA	0x0C000020


	>;


};



pinctrl_lpuart2: lpuart2grp {


	fsl,pins = <


		SC_P_UART2_RX_ADMA_UART2_RX	0x06000020


		SC_P_UART2_TX_ADMA_UART2_TX	0x06000020


	>;


};



pinctrl_usdhc1: usdhc1grp {


	fsl,pins = <


		SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041


		SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021


		SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021


		SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021


		SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021


		SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021


		SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021


		SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021


		SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021


		SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021


		SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000041


		SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021


		SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29	0x06000021


	>;


};



pinctrl_usdhc2: usdhc2grp {


	fsl,pins = <


		SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK	0x06000041


		SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD	0x00000021


		SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021


		SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021


		SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021


		SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021


		SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B	0x06000021


		//SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x06000021


		SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30	0x06000021


	>;


};



pinctrl_fec2: fec2grp {


	fsl,pins = <


		SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x000014a0


		SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD	0x000014a0


		SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD		0x000514a0



		SC_P_ENET0_MDC_CONN_ENET1_MDC                   0x00000060


		SC_P_ENET0_MDIO_CONN_ENET1_MDIO                 0x00000060



		SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN            0x00000060


		SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0            0x00000060


		SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1        0x00000060


		SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER        0x00000060


		SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL          0x00000060


		SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0        0x00000060


		SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1        0x00000060


		SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL         0x00000060	/* ERST: Reset pin */


	>;


};


};

+};



+&i2c0 {

clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c0>;
status = "okay";

+};



+&i2c1 {

clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c1>;
status = "okay";

+};



+&lpuart2 {

pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart2>;
status = "okay";

+};



+&usdhc1 {

pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
clock-frequency=<52000000>;
no-1-8-v;
bus-width = <8>;
non-removable;
status = "okay";

+};



+&gpio0 {

status = "okay";

+};



+&gpio1 {

status = "okay";

+};



+&gpio2 {

status = "okay";

+};



+&gpio3 {

status = "okay";

+};



+&gpio4 {

status = "okay";

+};



+&gpio5 {

status = "okay";

+};



+&fec1 {

status ="disabled";

+};



+&fec2 {

pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec2>;
phy-mode = "rmii";

phy-handle = <&ethphy1>;
fsl,magic-packet;
status = "okay";

mdio {
#address-cells = <1>;


#size-cells = <0>;



ethphy0: ethernet-phy@0 {


	compatible = "ethernet-phy-ieee802.3-c22";


	reg = <0>;


};


ethphy1: ethernet-phy@1 {


	compatible = "ethernet-phy-ieee802.3-c22";


	reg = <1>;


};


};

+};
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index d17760e..1f25e9c 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -60,11 +60,17 @@ config TARGET_IMX8QXP_MEK
   select BOARD_LATE_INIT
   select IMX8QXP
+config TARGET_GIEDI

bool "Support i.MX8QXP Capricorn Giedi board"
select BOARD_LATE_INIT
select IMX8QXP


endchoice
source "board/freescale/imx8qm_mek/Kconfig"
 source "board/freescale/imx8qxp_mek/Kconfig"
 source "board/toradex/apalis-imx8/Kconfig"
 source "board/toradex/colibri-imx8x/Kconfig"
+source "board/siemens/capricorn/Kconfig"
endif
diff --git a/board/siemens/capricorn/Kconfig b/board/siemens/capricorn/Kconfig
new file mode 100644
index 0000000..ed1f793
--- /dev/null
+++ b/board/siemens/capricorn/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_GIEDI



+config SYS_BOARD

default "capricorn"


+config SYS_VENDOR

default "siemens"


+config SYS_CONFIG_NAME

default "giedi"


+endif
diff --git a/board/siemens/capricorn/MAINTAINERS b/board/siemens/capricorn/MAINTAINERS
new file mode 100644
index 0000000..5d81aaf
--- /dev/null
+++ b/board/siemens/capricorn/MAINTAINERS
@@ -0,0 +1,9 @@
+CAPRICORN BOARD
+M:	Anatolij Gustschin agust@denx.de
+S:	Maintained
+F:	board/siemens/capricorn/
+F:	include/configs/capricorn-common.h
+F:	include/configs/giedi.h
+F:	include/configs/siemens-ccp-common.h
+F:	include/configs/siemens-env-common.h
+F:	configs/giedi_defconfig
diff --git a/board/siemens/capricorn/Makefile b/board/siemens/capricorn/Makefile
new file mode 100644
index 0000000..d5846cc
--- /dev/null
+++ b/board/siemens/capricorn/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2019 Siemens AG
+#



+obj-y += board.o



+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-y += ../common/factoryset.o
+endif
diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c
new file mode 100644
index 0000000..d73b88b
--- /dev/null
+++ b/board/siemens/capricorn/board.c
@@ -0,0 +1,443 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*


Copyright 2017-2019 NXP







Copyright 2019 Siemens AG






*/

+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <netdev.h>
+#include <env_internal.h>
+#include <fsl_esdhc_imx.h>
+#include <i2c.h>
+#include <led.h>
+#include <pca953x.h>
+#include <power-domain.h>
+#include <asm/gpio.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/sys_proto.h>
+#ifndef CONFIG_SPL
+#include <asm/arch-imx8/clock.h>
+#endif
+#include "../common/factoryset.h"



+#define GPIO_PAD_CTRL \

((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \


 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \


 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \


 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))




+#define ENET_NORMAL_PAD_CTRL \

((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \


 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \


 (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \


 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))




+#define UART_PAD_CTRL \

((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \


 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \


 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \


 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))




+static iomux_cfg_t uart2_pads[] = {

SC_P_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
SC_P_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),

+};



+static void setup_iomux_uart(void)
+{

imx8_iomux_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));

+}



+int board_early_init_f(void)
+{

/* Set UART clock root to 80 MHz */
sc_pm_clock_rate_t rate = SC_80MHZ;
int ret;

ret = sc_pm_setup_uart(SC_R_UART_0, rate);
ret |= sc_pm_setup_uart(SC_R_UART_2, rate);
if (ret)
return ret;



setup_iomux_uart();

return 0;

+}



+#define ENET_PHY_RESET	IMX_GPIO_NR(0, 3)
+#define ENET_TEST_1	IMX_GPIO_NR(0, 8)
+#define ENET_TEST_2	IMX_GPIO_NR(0, 9)



+/*#define ETH_IO_TEST*/
+static iomux_cfg_t enet_reset[] = {

SC_P_ESAI0_SCKT | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL),

+#ifdef ETH_IO_TEST

/* GPIO0.IO08 MODE3: TXD0 */
SC_P_ESAI0_TX4_RX1 | MUX_MODE_ALT(4) |
MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
/* GPIO0.IO09 MODE3: TXD1 */
SC_P_ESAI0_TX5_RX0 | MUX_MODE_ALT(4) |
MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),

+#endif
+};



+static void enet_device_phy_reset(void)
+{

int ret = 0;

imx8_iomux_setup_multiple_pads(enet_reset, ARRAY_SIZE(enet_reset));

ret = gpio_request(ENET_PHY_RESET, "enet_phy_reset");
if (!ret) {
gpio_direction_output(ENET_PHY_RESET, 1);


gpio_set_value(ENET_PHY_RESET, 0);


/* SMSC9303 TRM chapter 14.5.2 */


udelay(200);


gpio_set_value(ENET_PHY_RESET, 1);


} else {
printf("ENET RESET failed!\n");


}


+#ifdef ETH_IO_TEST

ret =  gpio_request(ENET_TEST_1, "enet_test1");
if (!ret) {
int i;



printf("ENET TEST 1!\n");


for (i = 0; i < 20; i++) {


	gpio_direction_output(ENET_TEST_1, 1);


	gpio_set_value(ENET_TEST_1, 0);


	udelay(50);


	gpio_set_value(ENET_TEST_1, 1);


	udelay(50);


}


gpio_free(ENET_TEST_1);


} else {
printf("GPIO for ENET TEST 1 failed!\n");


}
ret =  gpio_request(ENET_TEST_2, "enet_test2");
if (!ret) {
int i;



printf("ENET TEST 2!\n");


for (i = 0; i < 20; i++) {


	gpio_direction_output(ENET_TEST_2, 1);


	gpio_set_value(ENET_TEST_2, 0);


	udelay(50);


	gpio_set_value(ENET_TEST_2, 1);


	udelay(50);


}


gpio_free(ENET_TEST_2);


} else {
printf("GPIO for ENET TEST 2 failed!\n");


}

+#endif
+}



+int setup_gpr_fec(void)
+{

sc_ipc_t ipc_handle = -1;
sc_err_t err = 0;
unsigned int test;

/*
* TX_CLK_SEL: it controls a mux between clock coming from the pad 50M


* input pin and clock generated internally to connectivity subsystem


*	0: internal clock


*	1: external clock --->  your choice for RMII


*


* CLKDIV_SEL: it controls a div by 2 on the internal clock path à


*	it should be don’t care when using external clock


*	0: non-divided clock


*	1: clock divided by 2


* 50_DISABLE or 125_DISABLE:


*	it’s used to disable the clock tree going outside the chip


*	when reference clock is generated internally.


*	It should be don’t care when reference clock is provided


*	externally.


*	0: clock is enabled


*	1: clock is disabled


*


* SC_C_TXCLK		= 24,


* SC_C_CLKDIV		= 25,


* SC_C_DISABLE_50	= 26,


* SC_C_DISABLE_125	= 27,


*/



err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, 1);
if (err != SC_ERR_NONE)
printf("Error in setting up SC_C %d\n\r", SC_C_TXCLK);



sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test);
debug("TEST SC_C %d-->%d\n\r", SC_C_TXCLK, test);

err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, 0);
if (err != SC_ERR_NONE)
printf("Error in setting up SC_C %d\n\r", SC_C_CLKDIV);



sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, &test);
debug("TEST SC_C %d-->%d\n\r", SC_C_CLKDIV, test);

err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_50, 0);
if (err != SC_ERR_NONE)
printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_50);



sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test);
debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_50, test);

err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_125, 1);
if (err != SC_ERR_NONE)
printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_125);



sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test);
debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_125, test);

err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, 1);
if (err != SC_ERR_NONE)
printf("Error in setting up SC_C %d\n\r", SC_C_SEL_125);



sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, &test);
debug("TEST SC_C %d-->%d\n\r", SC_C_SEL_125, test);

return 0;

+}



+#if IS_ENABLED(CONFIG_FEC_MXC)
+#include <miiphy.h>
+int board_phy_config(struct phy_device *phydev)
+{

if (phydev->drv->config)
phydev->drv->config(phydev);



return 0;

+}



+#endif



+static int setup_fec(void)
+{

setup_gpr_fec();
/* Reset ENET PHY */
enet_device_phy_reset();
return 0;

+}



+void reset_cpu(ulong addr)
+{
+}



+#ifndef CONFIG_SPL_BUILD
+/* LED's */
+static int board_led_init(void)
+{

struct udevice *bus, *dev;
u8 pca_led[2] = { 0x00, 0x00 };
int ret;

/* init all GPIO LED's */
if (IS_ENABLED(CONFIG_LED))
led_default_state();



/* enable all leds on PCA9552 */
ret = uclass_get_device_by_seq(UCLASS_I2C, PCA9552_1_I2C_BUS, &bus);
if (ret) {
printf("ERROR: I2C get %d\n", ret);


return ret;


}

ret = dm_i2c_probe(bus, PCA9552_1_I2C_ADDR, 0, &dev);
if (ret) {
printf("ERROR: PCA9552 probe failed\n");


return ret;


}

ret = dm_i2c_write(dev, 0x16, pca_led, sizeof(pca_led));
if (ret) {
printf("ERROR: PCA9552 write failed\n");


return ret;


}

mdelay(1);
return ret;

+}
+#endif /* !CONFIG_SPL_BUILD */



+int checkboard(void)
+{

puts("Board: Capricorn\n");

build_info();
print_bootinfo();
return 0;

+}



+int board_init(void)
+{

setup_fec();
return 0;

+}



+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{

return 0;

+}
+#endif



+int board_mmc_get_env_dev(int devno)
+{

return devno;

+}



+static int check_mmc_autodetect(void)
+{

char *autodetect_str = env_get("mmcautodetect");

if (autodetect_str && (strcmp(autodetect_str, "yes") == 0))
return 1;



return 0;

+}



+/* This should be defined for each board */
+__weak int mmc_map_to_kernel_blk(int dev_no)
+{

return dev_no;

+}



+void board_late_mmc_env_init(void)
+{

char cmd[32];
char mmcblk[32];
u32 dev_no = mmc_get_env_dev();

if (!check_mmc_autodetect())
return;



env_set_ulong("mmcdev", dev_no);

/* Set mmcblk env */
sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
mmc_map_to_kernel_blk(dev_no));


env_set("mmcroot", mmcblk);

sprintf(cmd, "mmc dev %d", dev_no);
run_command(cmd, 0);

+}



+#ifndef CONFIG_SPL_BUILD
+int factoryset_read_eeprom(int i2c_addr);



+static int load_parameters_from_factoryset(void)
+{

int ret;

ret = factoryset_read_eeprom(EEPROM_I2C_ADDR);
if (ret)
return ret;



return factoryset_env_set();

+}



+int board_late_init(void)
+{

env_set("sec_boot", "no");

+#ifdef CONFIG_AHAB_BOOT

env_set("sec_boot", "yes");

+#endif



+#ifdef CONFIG_ENV_IS_IN_MMC

board_late_mmc_env_init();

+#endif

/* Init LEDs */
if (board_led_init())
printf("I2C LED init failed\n");



/* Set environment from factoryset */
if (load_parameters_from_factoryset())
printf("Loading factoryset parameters failed!\n");



return 0;

+}



+/* Service button */
+#define MAX_PIN_NUMBER			128
+#define BOARD_DEFAULT_BUTTON_GPIO	IMX_GPIO_NR(1, 31)



+unsigned char get_button_state(char * const envname, unsigned char def)
+{

int button = 0;
int gpio;
char *ptr_env;

/* If button is not found we take default */
ptr_env = env_get(envname);
if (!ptr_env) {
printf("Using default: %u\n", def);


gpio = def;


} else {
gpio = (unsigned char)simple_strtoul(ptr_env, NULL, 0);


if (gpio > MAX_PIN_NUMBER)


	gpio = def;


}

gpio_request(gpio, "");
gpio_direction_input(gpio);
if (gpio_get_value(gpio))
button = 1;


else
button = 0;



gpio_free(gpio);

return button;

+}



+/*


This command returns the status of the user button on



Input - none



Returns -	1 if button is held down



0 if button is not held down




*/

+static int
+do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{

int button = 0;

button = get_button_state("button_usr1", BOARD_DEFAULT_BUTTON_GPIO);

if (argc > 1)
printf("Button state: %u\n", button);



return button;

+}



+U_BOOT_CMD(

usrbutton, CONFIG_SYS_MAXARGS, 2, do_userbutton,
"Return the status of user button",
"[print]"

+);



+#define ERST	IMX_GPIO_NR(0, 3)



+static int
+do_eth_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{

gpio_request(ERST, "ERST");
gpio_direction_output(ERST, 0);
udelay(200);
gpio_set_value(ERST, 1);
return 0;

+}



+U_BOOT_CMD(

switch_rst, CONFIG_SYS_MAXARGS, 2, do_eth_reset,
"Reset eth phy",
"[print]"

+);
+#endif /* ! CONFIG_SPL_BUILD */
diff --git a/board/siemens/capricorn/imximage.cfg b/board/siemens/capricorn/imximage.cfg
new file mode 100644
index 0000000..8660e50
--- /dev/null
+++ b/board/siemens/capricorn/imximage.cfg
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*


Copyright 2018 NXP







Refer doc/README.imx8image for more details about how-to configure



and create imx8image boot image


*/


+#define __ASSEMBLY__



+/* Boot from SD, sector size 0x400 */
+BOOT_FROM SD 0x400
+/* SoC type IMX8QX */
+SOC_TYPE IMX8QX
+/* Append seco container image */
+APPEND ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU capricorn-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 spl/u-boot-spl.bin 0x00100000
diff --git a/board/siemens/capricorn/spl.c b/board/siemens/capricorn/spl.c
new file mode 100644
index 0000000..47fe86c
--- /dev/null
+++ b/board/siemens/capricorn/spl.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*


Copyright 2018 NXP







Copyright 2019 Siemens AG






*/

+#include <common.h>
+#include <spl.h>
+#include <dm.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>



+DECLARE_GLOBAL_DATA_PTR;



+void spl_board_init(void)
+{

struct udevice *dev;

uclass_find_first_device(UCLASS_MISC, &dev);

for (; dev; uclass_find_next_device(&dev)) {
if (device_probe(dev))


	continue;


}

arch_cpu_init();

board_early_init_f();

timer_init();

preloader_console_init();

+}



+void board_init_f(ulong dummy)
+{

/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));

/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);

board_init_r(NULL, 0);

+}
diff --git a/board/siemens/capricorn/uboot-container.cfg b/board/siemens/capricorn/uboot-container.cfg
new file mode 100644
index 0000000..8165811
--- /dev/null
+++ b/board/siemens/capricorn/uboot-container.cfg
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*


Copyright 2019 NXP


*/


+#define __ASSEMBLY__



+/* This file is to create a container image could be loaded by SPL */
+BOOT_FROM SD 0x400
+SOC_TYPE IMX8QX
+CONTAINER
+IMAGE A35 bl31.bin	0x80000000
+IMAGE A35 u-boot.bin	CONFIG_SYS_TEXT_BASE
diff --git a/board/siemens/common/factoryset.c b/board/siemens/common/factoryset.c
index 7715ddf..0d3701c 100644
--- a/board/siemens/common/factoryset.c
+++ b/board/siemens/common/factoryset.c
@@ -13,7 +13,9 @@
 #include <env_internal.h>
 #include <i2c.h>
 #include <asm/io.h>
+#if !CONFIG_IS_ENABLED(TARGET_GIEDI) && !CONFIG_IS_ENABLED(TARGET_DENEB)
 #include <asm/arch/cpu.h>
+#endif
 #include <asm/arch/sys_proto.h>
 #include <asm/unaligned.h>
 #include <net.h>
diff --git a/configs/giedi_defconfig b/configs/giedi_defconfig
new file mode 100644
index 0000000..5a26f54
--- /dev/null
+++ b/configs/giedi_defconfig
@@ -0,0 +1,99 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
+CONFIG_TARGET_GIEDI=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/siemens/capricorn/imximage.cfg"
+CONFIG_BOOTDELAY=3
+CONFIG_LOG=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press "<Esc><Esc>" to stop\n"
+CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
+CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8-giedi"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_DM_GPIO=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_MV88E61XX_SWITCH=y
+CONFIG_MV88E61XX_88E6020_FAMILY=y
+CONFIG_MV88E61XX_CPU_PORT=5
+CONFIG_MV88E61XX_PHY_PORTS=0x7
+CONFIG_MV88E61XX_FIXED_PORTS=0x0
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B050000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+# CONFIG_SPL_WDT is not set
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h
new file mode 100644
index 0000000..41b9005
--- /dev/null
+++ b/include/configs/capricorn-common.h
@@ -0,0 +1,190 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*


Copyright 2017-2018 NXP



Copyright 2019 Siemens AG


*/


+#ifndef __IMX8X_CAPRICORN_H
+#define __IMX8X_CAPRICORN_H



+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>



+#include "siemens-env-common.h"
+#include "siemens-ccp-common.h"



+/* SPL config */
+#ifdef CONFIG_SPL_BUILD



+#define CONFIG_SPL_MAX_SIZE		(124 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(1024 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR		0x800
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION		0



+#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK		0x013E000
+#define CONFIG_SPL_BSS_START_ADDR	0x00128000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x1000	/* 4 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x00120000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x3000	/* 12 KB */
+#define CONFIG_MALLOC_F_ADDR		0x00120000



+#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE



+#endif /* CONFIG_SPL_BUILD */



+#define CONFIG_FACTORYSET



+#undef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING		GENERATE_CCP_VERSION("01", "07")



+#define CONFIG_REMAKE_ELF



+#define CONFIG_BOARD_EARLY_INIT_F



+/* Commands */
+#define CONFIG_CMD_READ



+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_CRC32
+#undef CONFIG_BOOTM_NETBSD



+/* ENET Config */
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define FEC_QUIRK_ENET_MAC



+/* ENET1 connects to base board and MUX with ESAI */
+#define CONFIG_FEC_ENET_DEV		1
+#define CONFIG_FEC_MXC_PHYADDR		0x0
+#define CONFIG_ETHPRIME                "eth1"



+/* I2C Configuration */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_I2C_SPEED	400000
+/* EEPROM */
+#define  EEPROM_I2C_BUS		0 /* I2C0 */
+#define  EEPROM_I2C_ADDR	0x50
+/* PCA9552 */
+#define  PCA9552_1_I2C_BUS	1 /* I2C1 */
+#define  PCA9552_1_I2C_ADDR	0x60
+#endif /* !CONFIG_SPL_BUILD */



+/* AHAB */
+#ifdef CONFIG_AHAB_BOOT
+#define AHAB_ENV "sec_boot=yes\0"
+#else
+#define AHAB_ENV "sec_boot=no\0"
+#endif



+#define MFG_ENV_SETTINGS_DEFAULT \

"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
"rdinit=/linuxrc " \


"clk_ignore_unused "\


"\0" \


"kboot=booti\0"\
"bootcmd_mfg=run mfgtool_args;" \
"if iminfo ${initrd_addr}; then " \
"if test ${tee} = yes; then " \
"bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \


"else " \
"booti ${loadaddr} ${initrd_addr} ${fdt_addr}; " \


"fi; " \
"else " \
   "echo \"Run fastboot ...\"; fastboot 0; "  \


"fi;\0"


+/* Boot M4 */
+#define M4_BOOT_ENV \

"m4_0_image=m4_0.bin\0" \
"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} " \
	"${loadaddr} ${m4_0_image}\0" \


"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \


+#define CONFIG_MFG_ENV_SETTINGS \

MFG_ENV_SETTINGS_DEFAULT \
"initrd_addr=0x83100000\0" \
"initrd_high=0xffffffffffffffff\0" \
"emmc_dev=0\0"


+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \

CONFIG_MFG_ENV_SETTINGS \
M4_BOOT_ENV \
AHAB_ENV \
ENV_COMMON \
"script=boot.scr\0" \
"image=Image\0" \
"panel=NULL\0" \
"console=ttyLP2\0" \
"fdt_addr=0x83000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"cntr_addr=0x88000000\0" \
"cntr_file=os_cntr_signed.bin\0" \
"initrd_addr=0x83800000\0" \
"initrd_high=0xffffffffffffffff\0" \
"netdev=eth0\0" \
"nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw\0" \
"hostname=capricorn\0" \
ENV_EMMC \
ENV_NET


+#define CONFIG_BOOTCOMMAND \

"if usrbutton; then " \
"run flash_self_test; " \


"reset; " \


"fi;" \
"run flash_self;" \
"reset;"


+/* Default location for tftp and bootm */
+#define CONFIG_LOADADDR			0x80280000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_INIT_SP_ADDR		0x80200000



+/* Default environment is in SD */
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#define CONFIG_ENV_OFFSET_REDUND	CONFIG_ENV_SIZE
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG



+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_ENV



+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+#define CONFIG_SYS_MMC_ENV_PART		2	/* user area */



+/* On CCP board, USDHC1 is for eMMC */
+#define CONFIG_SYS_MMC_ENV_DEV		0   /* eMMC */
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* eMMC */



+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)



+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_2			0x880000000
+/* DDR3 board total DDR is 1 GB */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1 GB */
+#define PHYS_SDRAM_2_SIZE		0x00000000	/* 0 GB */



+#define CONFIG_SYS_MEMTEST_START	0xA0000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \

			 (PHYS_SDRAM_1_SIZE >> 2))




+/* Console buffer and boot args */
+#define CONFIG_SYS_CBSIZE		2048
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE



+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		8000000	/* 8MHz */



+#define BOOTAUX_RESERVED_MEM_BASE	0x88000000
+#define BOOTAUX_RESERVED_MEM_SIZE	SZ_128M /* Reserve from second 128MB */



+#endif /* __IMX8X_CAPRICORN_H */
diff --git a/include/configs/giedi.h b/include/configs/giedi.h
new file mode 100644
index 0000000..dabb1fb
--- /dev/null
+++ b/include/configs/giedi.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*


Copyright 2019 Siemens AG






*/


+#ifndef __GIEDI_H
+#define __GIEDI_H



+#include "capricorn-common.h"



+#undef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING		GENERATE_CCP_VERSION("01", "07")



+/* DDR3 board total DDR is 1 GB */
+#undef PHYS_SDRAM_1_SIZE
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1 GB */



+#endif /* __GIEDI_H */
diff --git a/include/configs/siemens-ccp-common.h b/include/configs/siemens-ccp-common.h
new file mode 100644
index 0000000..ad2a082
--- /dev/null
+++ b/include/configs/siemens-ccp-common.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* Be very careful updating CONFIG_IDENT_STRING


This string will control the update flow whether an U-Boot should be



updated or not. If the version of installed U-Boot (in flash) is smaller



than the version to be installed (from update file), an update will



be performed.







General rules:




First 4 characters ' ##v' or  IDENT_MAGIC represent kind of a magic number





to identify the following strings after easily. Don't change them!








First 2 digits after 'v' or CCP_MAJOR are updated with U-Boot version





change, e.g. from 2015.04 to 2018.03








Second 2 digits after '.' or CCP_MINOR are updated if we want to upgrade





U-Boot within an U-Boot version.


*/

+#define CCP_IDENT_MAGIC			" ##v"
+#define GENERATE_CCP_VERSION(MAJOR, MINOR)	CCP_IDENT_MAGIC MAJOR "." MINOR



diff --git a/include/configs/siemens-env-common.h b/include/configs/siemens-env-common.h
new file mode 100644
index 0000000..64ca0c5
--- /dev/null
+++ b/include/configs/siemens-env-common.h
@@ -0,0 +1,202 @@
+/* SPDX-License-Identifier: GPL-2.0+ */



+/* Common env settings */



+/** set_bootargs()


input:



console:	string, tty, etc.



baudrate:	string, tty baudrate



testargs:	string



optargs:	string



output:



bootargs:	string, default boot string


*/

+#define ENV_BOOTARGS_DEFAULT "set_bootargs=" \

"setenv bootargs " \
"console=${console} " \


"${testargs} " \


"${optargs}\0"




+/** set_bootargs_net()


input:



kernel_name:



dtb_name:



project_dir:



output:


*/

+#define ENV_NET_FCT_NETARGS "set_bootargs_net=" \

"run set_bootargs;" \
"setenv bootfile ${project_dir}/boot/${kernel_name};" \
"setenv bootdtb ${project_dir}/boot/${dtb_name_nfs}.dtb;" \
"setenv rootpath /home/projects/${project_dir}/;" \
"setenv bootargs ${bootargs} " \
"root=/dev/nfs " \


"nfsroot=${serverip}:${rootpath},${nfsopts} " \


"ip=${ipaddr}:${serverip}:" \


	"${gatewayip}:${netmask}:${hostname}:eth0:off\0"




+/** net_nfs()


input:



output:


*/

+#define ENV_NET_FCT_BOOT "net_nfs=" \

"echo Booting from network ...; " \
"run set_bootargs_net; " \
"tftpboot ${dtb_loadaddr} ${serverip}:${bootdtb};" \
"if test $? -eq 1;" \
"then " \
"echo Loading default.dtb!;" \


"tftpboot ${dtb_loadaddr} ${serverip}:${project_dir}/boot/${dtb_name_default}.dtb;" \


"fi;" \
"tftpboot ${kernel_loadaddr} ${serverip}:${bootfile};" \
"printenv bootargs;" \
"booti ${kernel_loadaddr} - ${dtb_loadaddr}\0"


+/** check_update()


input:



upgrade_available:	[0|1],	if set to 1 check bootcount variables



bootcount:		int,	bootcount



bootlimit:		int,	limit cootcount



toggle_partition():	-	toggles active partition set



output:



upgrade_available:	[0|1],	set to 0 if bootcount > bootlimit


*/

+#define ENV_FCT_CHECK_UPGRADE "check_upgrade="\

"if test ${upgrade_available} -eq 1; " \
"then " \
"echo  upgrade_available is set; " \


"if test ${bootcount} -gt ${bootlimit}; " \


"then " \


	"setenv upgrade_available 0;" \


	"echo toggle partition;" \


	"run toggle_partition;" \


"fi;" \


"fi;\0"


+/** toggle_partition()


input:



partitionset_active:	[A|B],	selected partition set



output:



partitionset_active:	[A|B],	toggle


*/

+#define ENV_FCT_TOGGLE_PARTITION "toggle_partition="\

"setenv ${partitionset_active} true;" \
"if test -n ${A}; " \
"then " \
"setenv partitionset_active B; " \


"env delete A; " \


"fi;" \
"if test -n ${B}; "\
"then " \
"setenv partitionset_active A; " \


"env delete B; " \


"fi;" \
"saveenv\0"


+/** set_partition()


input:



partitionset_active:	[A|B],	selected partition set



rootfs_name:		string,	mmc device file in kernel, e.g. /dev/mmcblk0



output:



mmc_active_vol:	string,	mmc partition device file in kernel, e.g. /dev/mmcblk0p2



mmc_part_nr:		int,	partition number of mmc, e.g. /dev/mmcblk0p2 --> 2


*/

+#define ENV_EMMC_FCT_SET_ACTIVE_PARTITION "set_partition=" \

"setenv ${partitionset_active} true;" \
"if test -n ${A}; " \
"then " \
"setenv mmc_part_nr 1;" \


"fi;" \
"if test -n ${B}; " \
"then " \
"setenv mmc_part_nr 2;" \


"fi;" \
"setenv mmc_active_vol ${rootfs_name}p${mmc_part_nr} \0"


+/** set_bootargs_mmc()


input:



bootargs:		string, default bootargs



mmc_active_vol		string, mmc partition device file in kernel, e.g. /dev/mmcblk0p2



ip_method:		string, [none|?]



output:



bootargs:		string


*/

+#define ENV_EMMC_FCT_SET_EMMC_BOOTARGS "set_bootargs_mmc=" \

"setenv bootargs ${bootargs} " \
"root=${mmc_active_vol} rw " \


"rootdelay=1 rootwait " \


"rootfstype=ext4 " \


"ip=${ip_method} \0"




+/** mmc_load_bootfiles()


input:



mmc_part_nr:



dtb_loadaddr:



dtb_name:



kernel_loadaddr:



kernel_name:


*/

+#define ENV_EMMC_FCT_LOADFROM_EMMC "mmc_load_bootfiles=" \

"echo Loading from eMMC ...;" \
"ext4load mmc 0:${mmc_part_nr} ${dtb_loadaddr} boot/${dtb_name}.dtb;" \
"if test $? -eq 1;" \
"then " \
"echo Loading default.dtb!;" \


"ext4load mmc 0:${mmc_part_nr} ${dtb_loadaddr} boot/${dtb_name_default}.dtb;" \


"fi;" \
"ext4load mmc 0:${mmc_part_nr} ${kernel_loadaddr} boot/${kernel_name};" \
"printenv bootargs;\0"


+/** mmc_boot()


input:



mmc_part_nr:



dtb_loadaddr:



dtb_name:



kernel_loadaddr:



kernel_name:


*/

+#define ENV_EMMC_FCT_EMMC_BOOT "mmc_boot=" \

"run set_bootargs;" \
"run check_upgrade; " \
"run set_partition;" \
"run set_bootargs_mmc;" \
"run mmc_load_bootfiles;" \
"echo Booting from eMMC ...; " \
"booti ${kernel_loadaddr} - ${dtb_loadaddr} \0"


+#define ENV_EMMC_ALIASES "" \

"flash_self=run mmc_boot\0" \
"flash_self_test=setenv testargs test; " \
"run mmc_boot\0"




+#define ENV_COMMON "" \

"project_dir=targetdir/rootfs\0" \
"serverip=192.168.251.2\0" \
"ipaddr=192.168.251.1\0" \
"dtb_name_nfs=default\0" \
"dtb_name_default=default\0" \
"kernel_name=Image\0" \
"partitionset_active=A\0" \
"dtb_loadaddr=0x83000000\0" \
"kernel_loadaddr=0x80280000\0" \
"ip_method=none\0" \
"rootfs_name=/dev/mmcblk0\0" \
"upgrade_available=0\0" \
"bootlimit=3\0" \
"altbootcmd=run bootcmd\0" \
"optargs=\0" \


+/**********************************************************************/



+#define ENV_EMMC	ENV_EMMC_FCT_EMMC_BOOT \

	ENV_EMMC_FCT_LOADFROM_EMMC \


	ENV_EMMC_FCT_SET_EMMC_BOOTARGS \


	ENV_EMMC_FCT_SET_ACTIVE_PARTITION \


	ENV_FCT_CHECK_UPGRADE \


	ENV_EMMC_ALIASES \


	ENV_FCT_TOGGLE_PARTITION




+#define ENV_NET		ENV_NET_FCT_BOOT \

	ENV_NET_FCT_NETARGS \


	ENV_BOOTARGS_DEFAULT




-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================



    

Re: [PATCH 1/2] imx: add imx8x capricorn giedi board

Stefano Babic

Signed-off-by: Anatolij Gustschin agust@denx.de