This patch adds support for the PM9261 board of Ronetix GmbH (www.ronetix.at)
Signed-off-by: Ilko Iliev iliev@ronetix.at --- MAKEALL | 1 + Makefile | 3 + board/ronetix/pm9261/Makefile | 60 +++++ board/ronetix/pm9261/config.mk | 1 + board/ronetix/pm9261/pm9261.c | 352 +++++++++++++++++++++++++ board/ronetix/pm9261/pm9261_led.c | 79 ++++++ board/ronetix/pm9261/pm9261_lowlevel_init.S | 368 +++++++++++++++++++++++++++ board/ronetix/pm9261/pm9261_nand.c | 79 ++++++ board/ronetix/pm9261/pm9261_partition.c | 47 ++++ include/configs/pm9261.h | 266 ++++++++++++++++++++ 10 files changed, 1265 insertions(+), 0 deletions(-) mode change 100755 => 100644 MAKEALL create mode 100644 board/ronetix/pm9261/Makefile create mode 100644 board/ronetix/pm9261/config.mk create mode 100644 board/ronetix/pm9261/pm9261.c create mode 100644 board/ronetix/pm9261/pm9261_led.c create mode 100644 board/ronetix/pm9261/pm9261_lowlevel_init.S create mode 100644 board/ronetix/pm9261/pm9261_nand.c create mode 100644 board/ronetix/pm9261/pm9261_partition.c create mode 100644 include/configs/pm9261.h
diff --git a/MAKEALL b/MAKEALL old mode 100755 new mode 100644 index a1df37b..09ba6d1 --- a/MAKEALL +++ b/MAKEALL @@ -545,6 +545,7 @@ LIST_at91=" \ kb9202 \ mp2usb \ m501sk \ + pm9261 \ pm9263 \ "
diff --git a/Makefile b/Makefile index 7d43159..0a5d3a9 100644 --- a/Makefile +++ b/Makefile @@ -2561,6 +2561,9 @@ at91cap9adk_config : unconfig at91sam9260ek_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9260ek atmel at91
+pm9261_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs pm9261 ronetix at91 + pm9263_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91
diff --git a/board/ronetix/pm9261/Makefile b/board/ronetix/pm9261/Makefile new file mode 100644 index 0000000..48a42ea --- /dev/null +++ b/board/ronetix/pm9261/Makefile @@ -0,0 +1,60 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop stelian.pop@leadtechdesign.com +# Lead Tech Design <www.leadtechdesign.com> +# Ilko Iliev <www.ronetix.at> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += pm9261.o +COBJS-y += pm9261_led.o +COBJS-y += pm9261_partition.o +COBJS-$(CONFIG_CMD_NAND) += pm9261_nand.o + +SOBJS := pm9261_lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $@, $(OBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ronetix/pm9261/config.mk b/board/ronetix/pm9261/config.mk new file mode 100644 index 0000000..7185419 --- /dev/null +++ b/board/ronetix/pm9261/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x23f00000 \ No newline at end of file diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c new file mode 100644 index 0000000..632eab1 --- /dev/null +++ b/board/ronetix/pm9261/pm9261.c @@ -0,0 +1,352 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop stelian.pop@leadtechdesign.com + * Lead Tech Design <www.leadtechdesign.com> + * Ilko Iliev <www.ronetix.at> +* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/sizes.h> +#include <asm/arch/at91sam9261.h> +#include <asm/arch/at91sam9261_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> +#include <lcd.h> +#include <dataflash.h> +#include <atmel_lcdc.h> +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000) +#include <net.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +static void pm9261_serial_hw_init(void) +{ +#ifdef CONFIG_USART0 + at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0); +#endif + +#ifdef CONFIG_USART1 + at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1); +#endif + +#ifdef CONFIG_USART2 + at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2); +#endif + +#ifdef CONFIG_USART3 /* DBGU */ + at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */ + at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); +#endif +} + +#ifdef CONFIG_CMD_NAND +static void pm9261_nand_hw_init(void) +{ + unsigned long csa; + + /* Enable CS3 */ + csa = at91_sys_read(AT91_MATRIX_EBICSA); + at91_sys_write(AT91_MATRIX_EBICSA, + csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + + /* Configure SMC CS3 for NAND/SmartMedia */ + at91_sys_write(AT91_SMC_SETUP(3), + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); + at91_sys_write(AT91_SMC_MODE(3), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | +#ifdef CFG_NAND_DBW_16 + AT91_SMC_DBW_16 | +#else /* CFG_NAND_DBW_8 */ + AT91_SMC_DBW_8 | +#endif + AT91_SMC_TDF_(2)); + + /* Configure RDY/BSY */ + at91_set_gpio_input(AT91_PIN_PA16, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(AT91_PIN_PC14, 1); + + at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ + at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */ +} +#endif + +#ifdef CONFIG_HAS_DATAFLASH +static void pm9261_spi_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PA3, 0); /* SPI0_NPCS0 */ + + at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ + at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ + at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0); +} +#endif + +#ifdef CONFIG_DRIVER_DM9000 +static void pm9261_dm9000_hw_init(void) +{ + /* Configure SMC CS2 for DM9000 */ + at91_sys_write(AT91_SMC_SETUP(2), + AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(2), + AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | + AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8)); + at91_sys_write(AT91_SMC_CYCLE(2), + AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)); + at91_sys_write(AT91_SMC_MODE(2), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | + AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | + AT91_SMC_TDF_(1)); + + /* Configure Interrupt pin as input, no pull-up */ + at91_set_gpio_input(AT91_PIN_PA24, 0); +} +#endif + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + vl_col: 240, + vl_row: 320, + vl_clk: 4965000, + vl_sync: ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + vl_bpix: 3, + vl_tft: 1, + vl_hsync_len: 5, + vl_left_margin: 1, + vl_right_margin:33, + vl_vsync_len: 1, + vl_upper_margin:1, + vl_lower_margin:0, + mmio: AT91SAM9261_LCDC_BASE, +}; + +void lcd_enable(void) +{ + at91_set_gpio_value(AT91_PIN_PA22, 0); /* power up */ +} + +void lcd_disable(void) +{ + at91_set_gpio_value(AT91_PIN_PA22, 1); /* power down */ +} + +static void pm9261_lcd_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ + at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ + at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */ + at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */ + at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */ + at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */ + at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */ + at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */ + at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ + at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ + + at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1); + + gd->fb_base = AT91SAM9261_SRAM_BASE; +} + +#ifdef CONFIG_LCD_INFO +#include <nand.h> +#include <version.h> + +extern flash_info_t flash_info[]; + +void lcd_show_board_info(void) +{ + ulong dram_size, nand_size, flash_size, dataflash_size; + int i; + char temp[32]; + + lcd_printf ("%s\n", U_BOOT_VERSION); + lcd_printf ("(C) 2008 Ronetix GmbH\n"); + lcd_printf ("support@ronetix.at\n"); + lcd_printf ("%s CPU at %s MHz", + AT91_CPU_NAME, + strmhz(temp, AT91_MAIN_CLOCK)); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + + nand_size = 0; + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + nand_size += nand_info[i].size; + + flash_size = 0; + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) + flash_size += flash_info[i].size; + + dataflash_size = 0; + for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++) + dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number * + dataflash_info[i].Device.pages_size; + + lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n" + "%ld MB DataFlash\n", + dram_size >> 20, + nand_size >> 20, + flash_size >> 20, + dataflash_size >> 20); +} +#endif /* CONFIG_LCD_INFO */ + +#endif /* CONFIG_LCD */ + +int board_init(void) +{ + /* Enable Ctrlc */ + console_init_f(); + + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC); + + /* arch number of AT91SAM9261EK-Board */ + gd->bd->bi_arch_number = MACH_TYPE_PM9261; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + pm9261_serial_hw_init(); +#ifdef CONFIG_CMD_NAND + pm9261_nand_hw_init(); +#endif +#ifdef CONFIG_HAS_DATAFLASH + pm9261_spi_hw_init(); +#endif +#ifdef CONFIG_DRIVER_DM9000 + pm9261_dm9000_hw_init(); +#endif +#ifdef CONFIG_LCD + pm9261_lcd_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +#ifdef CONFIG_DRIVER_DM9000 + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + eth_init(gd->bd); +#endif +} +#endif + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard (void) +{ + uint32_t reg, diva, divb, mula, mulb; + uint32_t val, mdiv, pres, usbdiv, crystal; + char buf[32]; + + reg = at91_sys_read(AT91_CKGR_PLLAR); + mula = ((reg >> 16) & 0x7FF) + 1; + diva = reg & 0xFF; + + reg = at91_sys_read(AT91_CKGR_PLLBR); + mulb = ((reg >> 16) & 0x7FF) + 1; + divb = reg & 0xFF; + usbdiv = (reg >> 28) & 0x3; + + reg = at91_sys_read(AT91_PMC_MCKR); + mdiv = (reg >> 8) & 3; + pres = (reg >> 2) & 7; + +#ifdef USE_CALCULATED_CRYSTAL_FREQ + reg = at91_sys_read(AT91_CKGR_MCFR); + val = (reg & 0xFFFF) * AT91_SLOW_CLOCK / 16; +#else + crystal = PM9261_CRYSTAL; +#endif + + printf ("Board : Ronetix PM9261\n"); + printf ("Crystal frequency: %8s MHz\n", strmhz(buf,crystal)); + + val = (crystal * mula) / diva; + printf ("CPU clock : %8s MHz\n", strmhz(buf, val)); + + val /= (1 << pres); + val /= (1 << mdiv); + printf ("Master clock : %8s MHz\n", strmhz(buf, val)); + + val = (crystal * mulb) / divb; + val /= (1 << usbdiv); + printf ("USB clock : %8s MHz\n", strmhz(buf, val) ); + + printf ("\n"); + return 0; +} +#endif diff --git a/board/ronetix/pm9261/pm9261_led.c b/board/ronetix/pm9261/pm9261_led.c new file mode 100644 index 0000000..bf55512 --- /dev/null +++ b/board/ronetix/pm9261/pm9261_led.c @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop stelian.pop@leadtechdesign.com + * Lead Tech Design <www.leadtechdesign.com> + * Ilko Iliev <www.ronetix.at> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/at91sam9261.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> + +#define RED_LED AT91_PIN_PC12 +#define GREEN_LED AT91_PIN_PC13 +#define YELLOW_LED AT91_PIN_PC15 + +void red_LED_on(void) +{ + at91_set_gpio_value(RED_LED, 1); +} + +void red_LED_off(void) +{ + at91_set_gpio_value(RED_LED, 0); +} + +void green_LED_on(void) +{ + at91_set_gpio_value(GREEN_LED, 0); +} + +void green_LED_off(void) +{ + at91_set_gpio_value(GREEN_LED, 1); +} + +void yellow_LED_on(void) +{ + at91_set_gpio_value(YELLOW_LED, 0); +} + +void yellow_LED_off(void) +{ + at91_set_gpio_value(YELLOW_LED, 1); +} + + +void coloured_LED_init(void) +{ + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC); + + at91_set_gpio_output(RED_LED, 1); + at91_set_gpio_output(GREEN_LED, 1); + at91_set_gpio_output(YELLOW_LED, 1); + + at91_set_gpio_value(RED_LED, 0); + at91_set_gpio_value(GREEN_LED, 1); + at91_set_gpio_value(YELLOW_LED, 1); +} diff --git a/board/ronetix/pm9261/pm9261_lowlevel_init.S b/board/ronetix/pm9261/pm9261_lowlevel_init.S new file mode 100644 index 0000000..619844b --- /dev/null +++ b/board/ronetix/pm9261/pm9261_lowlevel_init.S @@ -0,0 +1,368 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * + * Modified for the Ronetix PM9261 board + * (C) Copyright 2008 Ronetix GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/hardware.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_pio.h> + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + +#define SDRAM 0x20000000 /* address of the SDRAM */ + +/* clocks */ +#define MOR_VAL 0x00002001 /* CKGR_MOR - enable main osc. */ +#define PLLAR_VAL (0x2000B000 | ((MASTER_PLL_MUL - 1)<< 16) | (MASTER_PLL_DIV)) +/* #define PLLAR_VAL 0x200CBF01 */ /* 239.616000 MHz for PCK */ +#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz for USB) */ + +#define MCKR_VAL 0x00000102 /* PCK/2 = MCK Master Clock from PLLA*/ + +#define AT91_WDTC_WDMR 0xFFFFFD44 /* (WDTC) Watchdog Mode Register */ +#define WDTC_WDMR_VAL 0x3fff8fff /* disable watchdog */ +#define PIOC_PDR_VAL1 0xFFFF0000 /* define PDC[31:16] as DATA[31:16] */ +#define PIOC_PPUDR_VAL 0xFFFF0000 /* no pull-up for D[31:16] */ +#define MATRIX_EBICSA_VAL 0x10A /* EBI_CSA, no pull-ups for D[15:0], + CS1 SDRAM, CS3 NAND Flash */ + +#define AT91_PIOC_PDR (AT91_BASE_SYS + AT91_PIOC + PIO_PDR) +#define AT91_PIOC_PPUDR (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR) +#define AT91_PIOC_ASR (AT91_BASE_SYS + AT91_PIOC + PIO_ASR) +#define AT91_PIOC_BSR (AT91_BASE_SYS + AT91_PIOC + PIO_BSR) +#define AT91_PIOC_PER (AT91_BASE_SYS + AT91_PIOC + PIO_PER) +#define AT91_PIOC_OER (AT91_BASE_SYS + AT91_PIOC + PIO_OER) +#define AT91_PIOC_SODR (AT91_BASE_SYS + AT91_PIOC + PIO_SODR) +#define AT91_MATRIX_EBICSA (0xFFFFEE30) + +#define AT91_SMC_CTRL0 (0xFFFFEC0C) /* (SMC) Control Register for CS 0 */ +#define AT91_SMC_CYCLE0 (0xFFFFEC08) /* (SMC) Cycle Register for CS 0 */ +#define AT91_SMC_SETUP0 (0xFFFFEC00) /* (SMC) Setup Register for CS 0 */ +#define AT91_SMC_PULSE0 (0xFFFFEC04) /* (SMC) Pulse Register for CS 0 */ + +#define AT91_SMC_CTRL3 (0xFFFFEC3C) /* (SMC) Control Register for CS 0 */ +#define AT91_SMC_CYCLE3 (0xFFFFEC38) /* (SMC) Cycle Register for CS 0 */ +#define AT91_SMC_SETUP3 (0xFFFFEC30) /* (SMC) Setup Register for CS 0 */ +#define AT91_SMC_PULSE3 (0xFFFFEC34) /* (SMC) Pulse Register for CS 0 */ + +#define AT91_SDRAMC_CR (0xFFFFEA08) /* (SDRAMC0) SDRAM Configuration Reg.*/ +#define AT91_SDRAMC_MR (0xFFFFEA00) /* (SDRAMC0) SDRAM Mode Register */ +#define AT91_SDRAMC_MDR (0xFFFFEA24) /* (SDRAMC0) SDRAM Memory Device Reg.*/ +#define AT91_SDRAMC_TR (0xFFFFEA04) /* (SDRAMC0) SDRAM Refresh Timer Reg.*/ + +#define AT91_RSTC_RMR (0xFFFFFD08) /* (RSTC) Reset Mode Register */ + +/* SDRAM */ +#define SDRC_MR_VAL1 0 /* SDRAMC_MR Mode register */ +#define SDRC_TR_VAL1 0x13C /* SDRAMC_TR - Refresh Timer register*/ +#define SDRC_CR_VAL 0x85237279 /* SDRAMC_CR - Configuration register*/ +#define SDRC_MDR_VAL 0 /* Memory Device Register -> SDRAM */ +#define SDRC_MR_VAL2 0x00000002 /* SDRAMC_MR */ +#define SDRAM_VAL1 0 /* SDRAM_BASE */ +#define SDRC_MR_VAL3 4 /* SDRC_MR */ +#define SDRAM_VAL2 0 /* SDRAM_BASE */ +#define SDRAM_VAL3 0 /* SDRAM_BASE */ +#define SDRAM_VAL4 0 /* SDRAM_BASE */ +#define SDRAM_VAL5 0 /* SDRAM_BASE */ +#define SDRAM_VAL6 0 /* SDRAM_BASE */ +#define SDRAM_VAL7 0 /* SDRAM_BASE */ +#define SDRAM_VAL8 0 /* SDRAM_BASE */ +#define SDRAM_VAL9 0 /* SDRAM_BASE */ +#define SDRC_MR_VAL4 3 /* SDRC_MR */ +#define SDRAM_VAL10 0 /* SDRAM_BASE */ +#define SDRC_MR_VAL5 0 /* SDRC_MR */ +#define SDRAM_VAL11 0 /* SDRAM_BASE */ +#define SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define SDRAM_VAL12 0 /* SDRAM_BASE */ + +/* setup CS0 (NOR Flash) - 16-bit, 15 WS */ +#define SMC_SETUP0_VAL 0x0A0A0A0A /* SMC_SETUP */ +#define SMC_PULSE0_VAL 0x0B0B0B0B /* SMC_PULSE */ +#define SMC_CYCLE0_VAL 0x00160016 /* SMC_CYCLE */ +#define SMC_CTRL0_VAL 0x00161003 /* SMC_MODE */ + +/* setup CS3 (NAND Flash) - 16-bit */ +#define SMC_SETUP3_VAL 0x03030303 /* SMC_SETUP */ +#define SMC_PULSE3_VAL 0x04040404 /* SMC_PULSE */ +#define SMC_CYCLE3_VAL 0x00080008 /* SMC_CYCLE */ +#define SMC_CTRL3_VAL 0x00161003 /* SMC_MODE */ + +/* NAND FLash: configure PIOs in periph mode */ +#define PIOC_ASR_VAL 3 /* PIOC->ASR <- PC0 | PC1 */ +#define PIOC_BSR_VAL 0 /* PIOC->BSR */ +#define PIOC_PDR_VAL2 3 /* PIOC->PDR <- PC0 | PC1 */ +#define PIOC_PER_VAL 0x4000 +#define PIOC_OER_VAL 0x4000 /* PIOC->PER <- PC14 */ +#define PIOC_SODR_VAL 0x4000 /* PIOC->SODR, set PC14 to '1' */ + +#define RSTC_RMR_VAL 0xA5000301 /* user reset enable */ + +_TEXT_BASE: + .word TEXT_BASE + +.globl lowlevel_init +lowlevel_init: + + mov r5, pc /* r5 = POS1 + 4 current */ +POS1: + ldr r0, =POS1 /* r0 = POS1 compile */ + ldr r2, _TEXT_BASE + sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */ + sub r5, r5, r0 /* r0 = TEXT_BASE-1 */ + sub r5, r5, #4 /* r1 = text base - current */ + + /* memory control configuration 1 */ + ldr r0, =SMRDATA + ldr r2, =SMRDATA1 + ldr r1, _TEXT_BASE + sub r0, r0, r1 + sub r2, r2, r1 + add r0, r0, r5 + add r2, r2, r5 +0: + /* the address */ + ldr r1, [r0], #4 + /* the value */ + ldr r3, [r0], #4 + str r3, [r1] + cmp r2, r0 + bne 0b + +/*----------------------------------------------------------------------------- +;PMC Init Step 1. +;------------------------------------------------------------------------------ +;- Check if the PLL is already initialized +;----------------------------------------------------------------------------*/ + ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) + ldr r0, [r1] + and r0, r0, #3 + cmp r0, #0 + bne setup_PLLB + +/*;--------------------------------------------------------------------------- +;- Enable the Main Oscillator +;----------------------------------------------------------------------------*/ + ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR) + ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR) + /* Main oscillator Enable register PMC_MOR: */ + /* Enable main oscillator, OSCOUNT = 0xFF */ + ldr r0, =0x0000FF01 + str r0, [r1] + + /* Reading the PMC Status to detect when the Main Oscillator is enabled */ + mov r4, #AT91_PMC_MOSCS +MOSCS_Loop: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_MOSCS + bne MOSCS_Loop + +/*----------------------------------------------------------------------------- +;PMC Init Step 2. +;------------------------------------------------------------------------------ +;- Setup PLLA +;----------------------------------------------------------------------------*/ + ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR) + /* (18.432MHz/1)*13 = 239 MHz */ + ldr r0, =PLLAR_VAL + str r0, [r1] + + /* Reading the PMC Status register to detect when the PLLA is locked */ + mov r4, #AT91_PMC_LOCKA +MOSCS_Loop1: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_LOCKA + bne MOSCS_Loop1 + +/*----------------------------------------------------------------------------- +;PMC Init Step 3. +;------------------------------------------------------------------------------ +;- Switch on the Main Oscillator 18.432 MHz +;----------------------------------------------------------------------------*/ + ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) + + /* -Master Clock Controller register PMC_MCKR */ + ldr r0, =0x102 + str r0, [r1] + + /* Reading the PMC Status to detect when the Master clock is ready */ + mov r4, #AT91_PMC_MCKRDY +MCKRDY_Loop: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_MCKRDY + bne MCKRDY_Loop + +/*----------------------------------------------------------------------------- +;PMC Init Step 4. +;------------------------------------------------------------------------------ +;- Setup PLLB +;----------------------------------------------------------------------------*/ +setup_PLLB: + ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR) + mov r4, #AT91_PMC_LOCKB + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_LOCKB + beq PLL_setup_end + + ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLBR) + /* 48.054857 MHz =18432000*72/14/2 for USB) */ + ldr r0, =PLLBR_VAL + str r0, [r1] + + /* Reading the PMC Status register to detect when the PLLB is locked */ + mov r4, #AT91_PMC_LOCKB +MOSCS_Loop2: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_LOCKB + bne MOSCS_Loop2 + +PLL_setup_end: + + /* memory control configuration 2 */ + ldr r0, =AT91_SDRAMC_TR + ldr r1, [r0] + cmp r1, #0 + bne SDRAM_setup_end + + ldr r0, =SMRDATA1 + ldr r2, =SMRDATA2 + ldr r1, _TEXT_BASE + sub r0, r0, r1 + sub r2, r2, r1 + add r0, r0, r5 + add r2, r2, r5 + +2: + /* the address */ + ldr r1, [r0], #4 + /* the value */ + ldr r3, [r0], #4 + str r3, [r1] + cmp r2, r0 + bne 2b + +SDRAM_setup_end: + /* everything is fine now */ + mov pc, lr + + .ltorg + +SMRDATA: + .word AT91_WDTC_WDMR + .word WDTC_WDMR_VAL + .word AT91_PIOC_PDR + .word PIOC_PDR_VAL1 + .word AT91_PIOC_PPUDR + .word PIOC_PPUDR_VAL + .word AT91_MATRIX_EBICSA + .word MATRIX_EBICSA_VAL + + .word AT91_SMC_SETUP0 + .word SMC_SETUP0_VAL + .word AT91_SMC_PULSE0 + .word SMC_PULSE0_VAL + .word AT91_SMC_CYCLE0 + .word SMC_CYCLE0_VAL + .word AT91_SMC_CTRL0 + .word SMC_CTRL0_VAL + .word AT91_SMC_SETUP3 + .word SMC_SETUP3_VAL + .word AT91_SMC_PULSE3 + .word SMC_PULSE3_VAL + .word AT91_SMC_CYCLE3 + .word SMC_CYCLE3_VAL + .word AT91_SMC_CTRL3 + .word SMC_CTRL3_VAL + + .word AT91_PIOC_ASR + .word PIOC_ASR_VAL + .word AT91_PIOC_BSR + .word PIOC_BSR_VAL + .word AT91_PIOC_PDR + .word PIOC_PDR_VAL2 + .word AT91_PIOC_PER + .word PIOC_PER_VAL + .word AT91_PIOC_OER + .word PIOC_OER_VAL + .word AT91_PIOC_SODR + .word PIOC_SODR_VAL + +SMRDATA1: + .word AT91_SDRAMC_MR + .word SDRC_MR_VAL1 + .word AT91_SDRAMC_TR + .word SDRC_TR_VAL1 + .word AT91_SDRAMC_CR + .word SDRC_CR_VAL + .word AT91_SDRAMC_MDR + .word SDRC_MDR_VAL + .word AT91_SDRAMC_MR + .word SDRC_MR_VAL2 + .word SDRAM + .word SDRAM_VAL1 + .word AT91_SDRAMC_MR + .word SDRC_MR_VAL3 + .word SDRAM + .word SDRAM_VAL2 + .word SDRAM + .word SDRAM_VAL3 + .word SDRAM + .word SDRAM_VAL4 + .word SDRAM + .word SDRAM_VAL5 + .word SDRAM + .word SDRAM_VAL6 + .word SDRAM + .word SDRAM_VAL7 + .word SDRAM + .word SDRAM_VAL8 + .word SDRAM + .word SDRAM_VAL9 + .word AT91_SDRAMC_MR + .word SDRC_MR_VAL4 + .word SDRAM + .word SDRAM_VAL10 + .word AT91_SDRAMC_MR + .word SDRC_MR_VAL5 + .word SDRAM + .word SDRAM_VAL11 + .word AT91_SDRAMC_TR + .word SDRC_TR_VAL2 + .word SDRAM + .word SDRAM_VAL12 + .word AT91_RSTC_RMR + .word RSTC_RMR_VAL + +SMRDATA2: + .word 0 + +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/board/ronetix/pm9261/pm9261_nand.c b/board/ronetix/pm9261/pm9261_nand.c new file mode 100644 index 0000000..9c609f0 --- /dev/null +++ b/board/ronetix/pm9261/pm9261_nand.c @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop stelian.pop@leadtechdesign.com + * Lead Tech Design <www.leadtechdesign.com> + * Ilko Iliev <www.ronetix.at> + * + * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/at91sam9261.h> +#include <asm/arch/gpio.h> +#include <asm/arch/at91_pio.h> + +#include <nand.h> + +/* + * hardware specific access to control-lines + */ +#define MASK_ALE (1 << 22) /* our ALE is AD22 */ +#define MASK_CLE (1 << 21) /* our CLE is AD21 */ + +static void pm9261_nand_hwcontrol(struct mtd_info *mtd, + int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + + if (ctrl & NAND_CTRL_CHANGE) { + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); + + if (ctrl & NAND_CLE) + IO_ADDR_W |= MASK_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= MASK_ALE; + + at91_set_gpio_value(AT91_PIN_PC14, !(ctrl & NAND_NCE)); + this->IO_ADDR_W = (void *) IO_ADDR_W; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +static int pm9261_nand_ready(struct mtd_info *mtd) +{ + return at91_get_gpio_value(AT91_PIN_PA16); +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->ecc.mode = NAND_ECC_SOFT; +#ifdef CFG_NAND_DBW_16 + nand->options = NAND_BUSWIDTH_16; +#endif + nand->cmd_ctrl = pm9261_nand_hwcontrol; + nand->dev_ready = pm9261_nand_ready; + nand->chip_delay = 20; + + return 0; +} diff --git a/board/ronetix/pm9261/pm9261_partition.c b/board/ronetix/pm9261/pm9261_partition.c new file mode 100644 index 0000000..95ac398 --- /dev/null +++ b/board/ronetix/pm9261/pm9261_partition.c @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2008 + * Ulf Samuelsson ulf@atmel.com + * Ilko Iliev <www.ronetix.at> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include <common.h> +#include <config.h> +#include <asm/hardware.h> +#include <dataflash.h> + +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; + +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ +}; + +/*define the area offsets*/ +#ifdef CONFIG_SYS_USE_DATAFLASH +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, + {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, + {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, + {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, + {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, +}; +#else +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0x00000000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, ""}, +}; + +#endif diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h new file mode 100644 index 0000000..4c75caa --- /dev/null +++ b/include/configs/pm9261.h @@ -0,0 +1,266 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop stelian.pop@leadtechdesign.com + * Lead Tech Design <www.leadtechdesign.com> + * Ilko Iliev <www.ronetix.at> + * + * Configuation settings for the RONETIX PM9261 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91_CPU_NAME "AT91SAM9261" + +#define CONFIG_DISPLAY_BOARDINFO + +#define PM9261_CRYSTAL 18432000 +#define MASTER_PLL_DIV 15 +#define MASTER_PLL_MUL 162 +#define MAIN_PLL_DIV 2 + +#define AT91_MAIN_CLOCK (PM9261_CRYSTAL / MASTER_PLL_DIV * MASTER_PLL_MUL) +#define AT91_MASTER_CLOCK (AT91_MAIN_CLOCK / MAIN_PLL_DIV) +#define CONFIG_SYS_HZ 1000000 /* 1us resolution */ + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/ +#define CONFIG_PM9261 1 /* on a Ronetix PM9261 Board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +/* LCD */ +#define CONFIG_LCD 1 +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO 1 +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO 1 +#define CONFIG_LCD_INFO_BELOW_LOGO 1 +#define CONFIG_SYS_WHITE_ON_BLACK 1 +#define CONFIG_ATMEL_LCD 1 +#define CONFIG_ATMEL_LCD_BGR555 1 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_USB 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +/* DataFlash */ +#define CONFIG_HAS_DATAFLASH 1 +#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) +#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */ +#define AT91_SPI_CLK 15000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* NAND flash */ +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +#undef CONFIG_SYS_NAND_DBW_16 + +/* NOR flash */ +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define PHYS_FLASH_1 0x10000000 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +/* Ethernet */ +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x30000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE + 4) +#define CONFIG_DM9000_USE_16BIT 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R 1 + +/* USB */ +#define CONFIG_USB_OHCI_NEW 1 +#define LITTLEENDIAN 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE 1 + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END 0x23e00000 + +#undef CONFIG_SYS_USE_DATAFLASH_CS0 +#undef CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SYS_USE_FLASH 1 + +#ifdef CONFIG_SYS_USE_DATAFLASH_CS0 + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CONFIG_ENV_IS_IN_DATAFLASH 1 +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) +#define CONFIG_ENV_OFFSET 0x4200 +#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x4200 +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 " \ + "mtdparts=at91_nand:-(root) " \ + "rw rootfstype=jffs2" + +#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */ + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_OFFSET 0x60000 +#define CONFIG_ENV_OFFSET_REDUND 0x80000 +#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock5 " \ + "mtdparts=at91_nand:128k(bootstrap)ro," \ + "256k(uboot)ro,128k(env1)ro," \ + "128k(env2)ro,2M(linux),-(root) " \ + "rw rootfstype=jffs2" + +#elif defined (CONFIG_SYS_USE_FLASH) + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_OVERWRITE 1 + +/* JFFS Partition offset set */ +#define CONFIG_SYS_JFFS2_FIRST_BANK 0 +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +/* 512k reserved for u-boot */ +#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 + +#define CONFIG_BOOTCOMMAND "run flashboot" + +#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand" +#define MTDPARTS_DEFAULT \ + "mtdparts=physmap-flash.0:" \ + "256k(u-boot)ro," \ + "64k(u-boot-env)ro," \ + "1408k(kernel)," \ + "-(rootfs);" \ + "nand:-(nand)" + +#define CONFIG_CON_ROT "fbcon=rotate:3 " +#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 " CONFIG_CON_ROT + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "partition=nand0,0\0" \ + "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + CONFIG_CON_ROT \ + "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ + ":$(hostname):eth0:off\0" \ + "ramboot=tftpboot 0x22000000 vmImage;" \ + "run ramargs;run addip;bootm 22000000\0" \ + "nfsboot=tftpboot 0x22000000 vmImage;" \ + "run nfsargs;run addip;bootm 22000000\0" \ + "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ + "" +#else +#error "Undefined memory device" +#endif + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "u-boot-pm9261> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif