Re: [U-Boot] [PATCH v6 1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox

On Mon, Aug 25, 2014 at 5:02 AM, Marek Vasut marex@denx.de wrote:

This $size here is used only by the cache flushing functions. We agreed in the previous iterations, that the cacheline is 32b on MX6SX . This change is pointless unless ARCH_DMA_MINALIGN != 32 on MX6SX. Is that right ?

Yes, you are right. The cacheline on mx6sx is 32 bytes. It is only the RX buffers that need 64-bytes alignment.

Will fix this in v7.

Thanks