This patch adds SD boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Alison Wang alison.wang@freescale.com Signed-off-by: Jason Jin jason.jin@freescale.com --- Makefile | 15 ++++- arch/arm/cpu/armv7/ls102xa/Makefile | 1 + arch/arm/cpu/armv7/ls102xa/spl.c | 35 +++++++++++ arch/arm/cpu/armv7/ls102xa/u-boot-spl.lds | 83 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-ls102xa/spl.h | 20 +++++++ board/freescale/common/qixis.h | 7 +++ board/freescale/ls1021aqds/ddr.c | 5 +- board/freescale/ls1021aqds/ls1021aqds.c | 31 ++++++++++ board/freescale/ls1021aqds/ls102xa_pbi.cfg | 8 +++ board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg | 14 +++++ boards.cfg | 1 + common/spl/spl_mmc.c | 2 + include/configs/ls1021aqds.h | 64 +++++++++++++++++++++ tools/pblimage.c | 20 +++++-- 14 files changed, 300 insertions(+), 6 deletions(-) create mode 100644 arch/arm/cpu/armv7/ls102xa/spl.c create mode 100644 arch/arm/cpu/armv7/ls102xa/u-boot-spl.lds create mode 100644 arch/arm/include/asm/arch-ls102xa/spl.h create mode 100644 board/freescale/ls1021aqds/ls102xa_pbi.cfg create mode 100644 board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg
diff --git a/Makefile b/Makefile index b8cce74..760e8b0 100644 --- a/Makefile +++ b/Makefile @@ -711,6 +711,7 @@ ALL-y += u-boot.srec u-boot.bin System.map binary_size_check ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin ifeq ($(CONFIG_SPL_FSL_PBL),y) ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin +ALL-$(CONFIG_SPL_PBL_PAD) += spl/u-boot-spl-pbl-pad.bin else ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl endif @@ -936,13 +937,25 @@ endif u-boot-img.bin: spl/u-boot-spl.bin u-boot.img FORCE $(call if_changed,cat)
+OBJCOPYFLAGS_u-boot-spl-pbl-pad.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_MAX_SIZE) \ + --gap-fill=0xff + +spl/u-boot-spl-pbl-pad.bin: spl/u-boot-spl.bin FORCE + $(call if_changed,pad_cat) + +ifdef CONFIG_SPL_PBL_PAD +SPLPBL_BINLOAD := spl/u-boot-spl-pbl-pad.bin +else +SPLPBL_BINLOAD := spl/u-boot-spl.bin +endif + #Add a target to create boot binary having SPL binary in PBI format #concatenated with u-boot binary. It is need by PowerPC SoC having #internal SRAM <= 512KB. MKIMAGEFLAGS_u-boot-spl.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
-spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE +spl/u-boot-spl.pbl: $(SPLPBL_BINLOAD) FORCE $(call if_changed,mkimage)
OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \ diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index d82ce8d..56ef3a7 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -10,3 +10,4 @@ obj-y += timer.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o +obj-$(CONFIG_SPL) += spl.o diff --git a/arch/arm/cpu/armv7/ls102xa/spl.c b/arch/arm/cpu/armv7/ls102xa/spl.c new file mode 100644 index 0000000..77ea1ee --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/spl.c @@ -0,0 +1,35 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> + +u32 spl_boot_device(void) +{ +#ifdef CONFIG_SPL_MMC_SUPPORT + return BOOT_DEVICE_MMC1; +#endif + return BOOT_DEVICE_NAND; +} + +u32 spl_boot_mode(void) +{ + switch (spl_boot_device()) { + case BOOT_DEVICE_MMC1: +#ifdef CONFIG_SPL_FAT_SUPPORT + return MMCSD_MODE_FAT; +#else + return MMCSD_MODE_RAW; +#endif + break; + case BOOT_DEVICE_NAND: + return 0; + break; + default: + puts("spl: error: unsupported device\n"); + hang(); + } +} diff --git a/arch/arm/cpu/armv7/ls102xa/u-boot-spl.lds b/arch/arm/cpu/armv7/ls102xa/u-boot-spl.lds new file mode 100644 index 0000000..86cbc6b --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/u-boot-spl.lds @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, garyj@denx.de + * + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + __image_copy_start = .; + CPUDIR/start.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*_i2c_*))); + } + + . = .; + + __image_copy_end = .; + + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + _end = .; + + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } + + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } +} + +#if defined(CONFIG_SPL_MAX_SIZE) +ASSERT(__image_copy_end - __image_copy_start < (CONFIG_SPL_MAX_SIZE), \ + "SPL image too big"); +#endif + +#if defined(CONFIG_SPL_BSS_MAX_SIZE) +ASSERT(__bss_end - __bss_start < (CONFIG_SPL_BSS_MAX_SIZE), \ + "SPL image BSS too big"); +#endif + +#if defined(CONFIG_SPL_MAX_FOOTPRINT) +ASSERT(__bss_end - _start < (CONFIG_SPL_MAX_FOOTPRINT), \ + "SPL image plus BSS too big"); +#endif diff --git a/arch/arm/include/asm/arch-ls102xa/spl.h b/arch/arm/include/asm/arch-ls102xa/spl.h new file mode 100644 index 0000000..26e4ea1 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/spl.h @@ -0,0 +1,20 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_SPL_H__ +#define __ASM_ARCH_SPL_H__ + +#define BOOT_DEVICE_NONE 0 +#define BOOT_DEVICE_XIP 1 +#define BOOT_DEVICE_XIPWAIT 2 +#define BOOT_DEVICE_NAND 3 +#define BOOT_DEVICE_ONENAND 4 +#define BOOT_DEVICE_MMC1 5 +#define BOOT_DEVICE_MMC2 6 +#define BOOT_DEVICE_MMC2_2 7 +#define BOOT_DEVICE_SPI 10 + +#endif /* __ASM_ARCH_SPL_H__ */ diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index d8fed14..204a3bd 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -100,8 +100,15 @@ u8 qixis_read_i2c(unsigned int reg); void qixis_write_i2c(unsigned int reg, u8 value); #endif
+#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CONFIG_SYS_I2C_FPGA_ADDR) +#define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg)) +#define QIXIS_WRITE(reg, value) \ + qixis_write_i2c(offsetof(struct qixis, reg), value) +#else #define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg)) #define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value) +#endif + #ifdef CONFIG_SYS_I2C_FPGA_ADDR #define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg)) #define QIXIS_WRITE_I2C(reg, value) \ diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c index bf05e34..5da85aa 100644 --- a/board/freescale/ls1021aqds/ddr.c +++ b/board/freescale/ls1021aqds/ddr.c @@ -156,9 +156,12 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size;
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) puts("Initializing DDR....using SPD\n"); dram_size = fsl_ddr_sdram(); - +#else + dram_size = fsl_ddr_sdram_size(); +#endif return dram_size; }
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index e8b3a82..3005975 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -13,6 +13,7 @@ #include <mmc.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> +#include <spl.h>
#include "../common/qixis.h" #include "ls1021aqds_qixis.h" @@ -29,10 +30,13 @@ enum { int checkboard(void) { char buf[64]; +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) u8 sw; +#endif
puts("Board: LS1021AQDS\n");
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) sw = QIXIS_READ(brdcfg[0]); sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
@@ -46,6 +50,7 @@ int checkboard(void) printf("IFCCard\n"); else printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); +#endif
printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", QIXIS_READ(id), QIXIS_READ(arch)); @@ -148,6 +153,32 @@ int board_early_init_f(void) return 0; }
+#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + + /* Set global data pointer */ + gd = &gdata; + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + get_clocks(); + + preloader_console_init(); + +#ifdef CONFIG_SPL_I2C_SUPPORT + i2c_init_all(); +#endif + out_le32(&cci->ctrl_ord, 0x00000008); + + dram_init(); + + board_init_r(NULL, 0); +} +#endif + int config_board_mux(int ctrl_type) { u8 reg12; diff --git a/board/freescale/ls1021aqds/ls102xa_pbi.cfg b/board/freescale/ls1021aqds/ls102xa_pbi.cfg new file mode 100644 index 0000000..edf9f94 --- /dev/null +++ b/board/freescale/ls1021aqds/ls102xa_pbi.cfg @@ -0,0 +1,8 @@ +#PBI commands + +#Configure Scratch register +09ee0200 10000000 +#Configure alternate space +09570158 00080000 +#Flush PBL data +096100c0 000FFFFF diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg new file mode 100644 index 0000000..e05ec16 --- /dev/null +++ b/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg @@ -0,0 +1,14 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 + +#enable IFC, disable QSPI and DSPI +#0608000a 00000000 00000000 00000000 +#00000000 00404000 60025a00 21042000 +#00200000 00000000 00000000 01038000 +#00000000 001b1200 00000000 00000000 + +#disable IFC, enable QSPI and DSPI +0608000a 00000000 00000000 00000000 +60000000 00407900 e0025a00 21046000 +00000000 00000000 00000000 00038000 +20024800 001b7200 00000000 00000000 diff --git a/boards.cfg b/boards.cfg index bf6656f..3e5e1d0 100644 --- a/boards.cfg +++ b/boards.cfg @@ -302,6 +302,7 @@ Active arm armv7 exynos samsung universal_c210 Active arm armv7 highbank - highbank highbank - Rob Herring robh@kernel.org Active arm armv7 keystone ti k2hk_evm k2hk_evm - Vitaly Andrianov vitalya@ti.com Active arm armv7 ls102xa freescale ls1021aqds ls1021aqds_nor ls1021aqds Alison Wang alison.wang@freescale.com +Active arm armv7 ls102xa freescale ls1021aqds ls1021aqds_sdcard ls1021aqds:RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT Alison Wang alison.wang@freescale.com Active arm armv7 ls102xa freescale ls1021atwr ls1021atwr_nor ls1021atwr Alison Wang alison.wang@freescale.com Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut marek.vasut@gmail.com Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg - diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index fa6f891..4937890 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -29,8 +29,10 @@ static int mmc_load_image_raw(struct mmc *mmc, unsigned long sector) if (err == 0) goto end;
+#ifndef CONFIG_SYS_SPL_ASSUME_UBOOT_NIH if (image_get_magic(header) != IH_MAGIC) return -1; +#endif
spl_parse_image_header(header);
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index a57b02b..4d70d41 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -40,8 +40,50 @@ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); #endif
+#if defined(CONFIG_SD_BOOT) || defined(CONFIG_QSPI_BOOT) +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 +#define CONFIG_QIXIS_I2C_ACCESS +#else #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#endif + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg +#define CONFIG_SPL +#define CONFIG_SPL_PBL_PAD +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/ls102xa/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x78 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 + +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0xd000 +#define CONFIG_SPL_STACK 0x1000f000 +#define CONFIG_SPL_PAD_TO 0xe000 +#define CONFIG_SYS_TEXT_BASE 0x82000000 + +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#define CONFIG_SYS_SPL_ASSUME_UBOOT_NIH +#define CONFIG_SYS_NO_FLASH +#endif
#ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x67f80000 @@ -72,6 +114,7 @@ unsigned long get_board_ddr_clk(void); /* * IFC Definitions */ +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) #define CONFIG_FSL_IFC #define CONFIG_SYS_FLASH_BASE 0x60000000 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE @@ -158,6 +201,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#endif
/* * QIXIS Definitions @@ -400,17 +444,37 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif
/* * Environment */ #define CONFIG_ENV_OVERWRITE
+#if defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET (1024 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_NAND_BOOT) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif
#define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP diff --git a/tools/pblimage.c b/tools/pblimage.c index 6e6e801..bfd1ecf 100644 --- a/tools/pblimage.c +++ b/tools/pblimage.c @@ -12,6 +12,10 @@ * Initialize to an invalid value. */ static uint32_t next_pbl_cmd = 0x82000000; +static uint32_t pbl_cmd_initaddr = 0x82000000; +static uint32_t pbi_crc_cmd1 = 0x13; +static uint32_t pbi_crc_cmd2 = 0x80; + /* * need to store all bytes in memory for calculating crc32, then write the * bytes to image file for PBL boot. @@ -49,7 +53,7 @@ static void init_next_pbl_cmd(FILE *fp_uboot) exit(EXIT_FAILURE); }
- next_pbl_cmd = 0x82000000 - st.st_size; + next_pbl_cmd = pbl_cmd_initaddr - st.st_size; }
static void generate_pbl_cmd(void) @@ -81,7 +85,7 @@ static void pbl_fget(size_t size, FILE *stream) static void load_uboot(FILE *fp_uboot) { init_next_pbl_cmd(fp_uboot); - while (next_pbl_cmd < 0x82000000) { + while (next_pbl_cmd < pbl_cmd_initaddr) { generate_pbl_cmd(); pbl_fget(64, fp_uboot); } @@ -111,6 +115,14 @@ static void pbl_parser(char *name) size_t len = 0;
fname = name; + + if (strstr(fname, "ls102xa")) { + next_pbl_cmd = 0x8100d000; + pbl_cmd_initaddr = 0x8100d000; + pbi_crc_cmd1 = 0x61; + pbi_crc_cmd2 = 0; + } + fd = fopen(name, "r"); if (fd == NULL) { printf("Error:%s - Can't open\n", fname); @@ -172,8 +184,8 @@ static void add_end_cmd(void)
/* Add PBI CRC command. */ *pmem_buf++ = 0x08; - *pmem_buf++ = 0x13; - *pmem_buf++ = 0x80; + *pmem_buf++ = pbi_crc_cmd1; + *pmem_buf++ = pbi_crc_cmd2; *pmem_buf++ = 0x40; pbl_size += 4;