Some boards need to access GPIOs to determine which SDRAM is fitted to the board, for example chromebook_link. Probe this device (if it exists) to make sure that this works as expected.
Signed-off-by: Simon Glass sjg@chromium.org ---
(no changes since v2)
Changes in v2: - Add new patch to make sure that the LPC is active before SDRAM init
arch/x86/lib/spl.c | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index 6886587f647..fb7dac68d7a 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -65,6 +65,8 @@ static int set_max_freq(void)
static int x86_spl_init(void) { + struct udevice *dev; + #ifndef CONFIG_TPL /* * TODO(sjg@chromium.org): We use this area of RAM for the stack @@ -109,6 +111,13 @@ static int x86_spl_init(void) return ret; } #endif + /* probe the LPC so we get the GPIO_BASE set up correctly */ + ret = uclass_first_device_err(UCLASS_LPC, &dev); + if (ret && ret != -ENODEV) { + log_debug("lpc probe failed\n"); + return ret; + } + ret = dram_init(); if (ret) { log_debug("dram_init() failed (err=%d)\n", ret);